XRT86VX38

T1/E1/J1 Framer/LIU Combo
Data Sheets OBS (Obsolete)

Overview

# of Channels 8
Data Rate(s) T1/E1/J1
Clk Rec Yes
SH/LH S/L
Temperature Range (°C) Ind
Op Pwr Sup/Max Cur 3.3V +/-5%
Package fpBGA-256, fpBGA-329
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The XRT86VX38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology (Reconfigurable, Relayless, Redundancy). The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VX38 provides protection from power failures and hot swapping.

The XRT86VX38 contains an integrated DS1/E1/J1 framer and LIU which provide DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be configured to frame to the common DS1/E1/J1 signal formats.

Each Framer block contains its own Transmit and Receive T1/E1/J1 Framing function. There are 3 Transmit HDLC controllers per channel which encapsulate contents of the Transmit HDLC buffers into LAPD Message frames. There are 3 Receive HDLC controllers per channel which extract the payload content of Receive LAPD Message frames from the incoming T1/E1/J1 data stream and write the contents into the Receive HDLC buffers. Each framer also contains a Transmit and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound T1/E1/J1 frames. Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access to the Data Link bits of the inbound T1/E1/J1 frames.

The XRT86VX38 fully meets all of the latest T1/E1/J1 specifications: ANSI T1/E1.107-1988, ANSI T1/E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/E1.408-1990, AT&T TR 62411 (12-90) TR54016, and ITU G-703, G.704, G706 and G.733, AT&T Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT G.704, JT G706, I.431. Extensive test and diagnostic functions include Loop-backs, Boundary scan, Pseudo Random bit sequence (PRBS) test pattern generation, Performance Monitor, Bit Error Rate (BER) meter, forced error insertion, and LAPD unchannelized data payload processing according to ITU-T standard Q.921.

  • Supports Section 13 - Synchronization Interface in ITU G.703 for both Transmit and Receive Paths
  • Supports SSM Synchronous Messaging Generation (BOC for T1, National Bits for E1) on the Transmit Path
  • Supports SSM Synchronous Messaging Extraction (BOC for T1, National Bits for E1) on the Receive Path
  • Supports BITS timing generation on the Transmit Outputs
  • Supports BITS timing extraction from NRZ data on the Analog Receive Path
  • DS-0 Monitoring on both Transmit and Receive Time Slots
  • Supports SSM Synchronization Messaging per ANSI T1.101-1999 and ITU G.704
  • Supports a Customized Section 13 - Synchronization Interface in G.703 at 1.544MHz
  • Independent, full duplex DS1 Tx and Rx Framer/LIUs
  • Each channel has full featured Long-haul/Short-haul LIU
  • Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz asynchronous back plane connections with jitter and wander attenuation
  • Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus
  • Programmable output clocks for Fractional T1/E1/J1
  • Supports Channel Associated Signaling (CAS)
  • Supports Common Channel Signalling (CCS)
  • Supports ISDN Primary Rate Interface (ISDN PRI) signaling
  • Extracts and inserts robbed bit signaling (RBS)
  • 3 Integrated HDLC controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1)
  • HDLC Controllers Support SS7
  • Timeslot assignable HDLC
  • V5.1 or V5.2 Interface
  • Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface every 1 second or for a single transmission
  • Supports SPRM and NPRM
  • Alarm Indication Signal with Customer Installation signature (AIS-CI)
  • Remote Alarm Indication with Customer Installation (RAI-CI)
  • Gapped Clock interface mode for Transmit and Receive.
  • Intel/Motorola and Power PC interfaces for configuration, control and status monitoring
  • Parallel search algorithm for fast frame synchronization
  • Wide choice of T1 framing structures: SF/D4, ESF, SLCR96, T1DM and N-Frame (non-signaling)
  • Direct access to D and E channels for fast transmission of data link information
  • Full BERT Controller for generation and detection on system and line side of the chip
  • PRBS, QRSS, and Network Loop Code generation and detection
  • Seven Independent, simultaneous Loop Code Detectors per Channel
  • Programmable Interrupt output pin
  • Supports programmed I/O and DMA modes of Read-Write access
  • The framer block encodes and decodes the T1/E1/J1 Frame serial data
  • Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms
  • Detects OOF, LOF, LOS errors and COFA conditions
  • Loopbacks: Local (LLB) and Line remote (LB)
  • Facilitates Inverse Multiplexing for ATM
  • Performance monitor with one second polling
  • Boundary scan (IEEE 1149.1) JTAG test port
  • Accepts external 8kHz Sync reference
  • 1.8V Inner Core
  • 3.3V CMOS operation with 5V tolerant inputs
  • 256-pin fpBGA and 329-pin fpBGA package with -40°C to +85°C operation

  • High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems
  • SONET/SDH terminal or Add/Drop multiplexers (ADMs)
  • T1/E1/J1 add/drop multiplexers (MUX)
  • Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1
  • BITS Timing
  • Digital Access Cross-connect System (DACs)
  • Digital Cross-connect Systems (DCS)
  • Frame Relay Switches and Access Devices (FRADS)
  • ISDN Primary Rate Interfaces (PRA)
  • PBXs and PCM channel bank
  • T3 channelized access concentrators and M13 MUX
  • Wireless base stations
  • ATM equipment with integrated DS1 interfaces
  • Multichannel DS1 Test Equipment
  • T1/E1/J1 Performance Monitoring
  • Voice over packet gateways
  • Routers

Documentation & Design Tools

Type Title Version Date File Size
Data Sheets XRT86VX38 E1 Register Description 1.0.4 October 2013 679.4 KB
Data Sheets XRT86VX38 T1 Register Description 1.0.4 October 2013 739.4 KB
Data Sheets XRT86VX38 Hardware Description 1.0.3 October 2013 302.5 KB
Application Notes TAN-072, E1 Software Customization for RLOS Compliance 1.0.0 January 2010 44.8 KB
Product Flyers T1/E1/J1 Eight - Channel Device July 2009 880.2 KB
Schematics & Design Files XRT86VX38ES_329 1 January 2009 73.8 KB
Schematics & Design Files XRT86VX38ES_256 0 July 2008 63.8 KB
Simulation Models
Package Type File
BGA
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Quality & RoHS

Part Number RoHS | Exempt RoHS Halogen Free REACH TSCA MSL Rating / Peak Reflow Package
XRT86VX38IB256 TBD TBD Y Y Y L4 / 245ᵒC fpBGA256
XRT86VX38IB256-F N Y Y Y Y L4 / 245ᵒC fpBGA256
XRT86VX38IB329 TBD TBD Y Y Y L4 / 245ᵒC fpBGA329

Click on the links above to download the Certificate of Non-Use of Hazardous Substances.

Additional Quality Documentation may be available, please Contact Support.

Parts & Purchasing

Part Number Pkg Code Min Temp Max Temp Status Suggested Replacement PDN
XRT86VX38IB256-F fpBGA256 -40 85 OBS
XRT86VX38IB329-F L-fpBGA329 -40 85 OBS XRT86VX38IB256-F
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Part Status Legend
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.

Packaging

Pkg Code Details Quantities Dimensions PDF
L-fpBGA329
  • JEDEC Reference: n/a
  • MSL Pb-Free: L4 @ 245ºC
  • MSL SnPb Eutectic: n/a
  • ThetaJA: 17.44ºC/W
  • Bulk Pack Style: n/a
  • Quantity per Bulk Pack: n/a
  • Quantity per Reel: n/a
  • Quantity per Tube: n/a
  • Quantity per Tray: 90
  • Reel Size (Dia. x Width x Pitch): n/a
  • Tape & Reel Unit Orientation: n/a
  • Dimensions: mm
  • Length: 17
  • Width: 17
  • Thickness: 1.57
  • Lead Pitch: 0.80
fpBGA256
  • JEDEC Reference: n/a
  • MSL Pb-Free: L4 @ 245ºC
  • MSL SnPb Eutectic: n/a
  • ThetaJA: 20.1ºC/W
  • Bulk Pack Style: Tray
  • Quantity per Bulk Pack: 90
  • Quantity per Reel: n/a
  • Quantity per Tube: n/a
  • Quantity per Tray: 90
  • Reel Size (Dia. x Width x Pitch): n/a
  • Tape & Reel Unit Orientation: n/a
  • Dimensions: mm
  • Length: 17
  • Width: 17
  • Thickness: 1.78
  • Lead Pitch: 1.00

Notifications

Distribution Date Description File
02/14/2022 MaxLinear has qualified Signetics, Korea, as an alternate assembly site for the product listed above. There is no change to datasheet form, fit, function.
09/30/2021 Product Discontinuation Notice
12/12/2018 Product Discontinuation Notice
07/12/2017 Product Discontinuation Notice
07/18/2014 Material Change. UTAC qualification to use mold compound KSG1250LKDS, in addition to current qualified mold compound KMC2520AL.
07/14/2014 Material Change. UTAC qualification to use mold compound KEG1250LKDS, in addition to current qualified mold compound KMC2520AL.
11/20/2013 Qualified copper wire bonding assembly and changed die revision from A to B. Material and design changes.

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The -F suffix indicates ROHS / Green compliance:
https://www.exar.com/quality-assurance-and-reliability/lead-free-program