MxL93684

The MxL93684 is a highly integrated PAM4 DSP SoC that enables 800Gbps optical interconnects using 100Gbps over a single optical wavelength (100G/λ).

The device has a high-speed electrical interface with eight transmit (Tx) and receive (Rx) input/output (I/O) that connect electrically through a module connector to the host ASIC. The device also has a high-speed optical side interface that has eight Tx and Rx I/O connecting through the optical components to optical fibers.

The electrical interface supports 106.25Gbps PAM4 signaling per lane over C2M host channels. The optical interface supports 106.25Gbps PAM4 signaling per wavelength for SR applications.

The device supports DSP functions including Line-side Tx digital pre-distortion (DPD), transmit pre-emphasis (TX FIR), receiver feed forward equalization (FFE) and decision feedback equalization (DFE).

The MxL93684, in a 12mm × 13mm package, includes integrated drivers with DC bias and modulation for vertical-cavity surface-emitting laser (VCSEL) based implementations. It offers exceptional signal integrity for signals in a compact footprint suitable for next generation optical module form-factors.

• 800G retimer capability that enables 800G VR8/SR8, 2×VR4/SR4

• 800G to 100G break-out mode

• Backward compatible to 8×53.125Gbps (PAM4) and 8×25.78125Gbps (NRZ) operating modes

• Support for mixed channel operating rates (that is, 4×106.25Gbps + 4×53.125Gbps)

• Full 8 × 8 crossbar functionality

• Tx equalization that includes pre-emphasis, digital pre-distortion, and reflection cancellation

• Rx equalization that includes CTLE, multi-tap FFE, and reflection cancellation

• Supports host channels with Nyquist loss in excess of 20dB

• Integrated crystal oscillator that eliminates the need for a costly reference clock source

• Small package size to enable the QSFP-DD800 space requirements

• Mission mode BER monitoring

• SNR/Histogram reporting for each receiver on both electrical and optical interfaces

• Diagnostic loop-back and test pattern generation and error checking

• SPI and I2C slave interface to communicate to module MCU

• SPI master for flash memory interface

• I2C master interface for TIA direct control

• Embedded CPU for real-time control

• Squelch function when loss of signal (LOS) or loss of lock (LOL) is detected

  
  

• QSFP-DD800 optical modules

• OSFP optical modules

• QSFP-DD800 AEC/ACC and AOC

• OSFP AEC/ACC and AOC