XRT86SH328

The XRT86SH328 is an integrated VT/TU Mapper with 28 port T1/E1 Line Interface Units. The XRT86SH328 contains integrated DS1/E1/J1 Framers for performance monitoring.

The XRT86SH328 processes the Section, Line and Path overhead in the SONET/SDH data-stream. The processing of path overhead bytes within the STS-1s or TUG-3s include 64 bytes (of buffer) for storing the (Section Trace and Path Trace) messages. Path Overhead bytes can be accessed either by on-chip registers or a Serial Output Port.

Each of the 28 T1 or E1 Channels use an internal De-Synchronizer circuit with an internal pointer leak algorithm. This removes the jitter due to mapping and pointer adjustments from the T1 or E1 signals that are de-mapped from the incoming SONET/SDH data-stream. These De-Synchronizer circuits do not need any external clock references for its operation.

The Transmit Blocks permit flexible insertion of TOH and POH bytes via both Hardware and Software control.

The Receive Blocks receive a SONET STS-1 signals or an SDH STM-1 signal and performs the necessary Transport and Path Overhead Processing.

A PRBS Pattern Generator and Receiver is implemented within each of the 28 T1/E1 channels in order to implement and measure Bit-Error performance.

A general purpose Microprocessor Interface is included for control, configuration and monitoring.

• Provides mapping of up to 28 T1 streams as Asynchronous VT1.5 into an STS-1 SPE or TU-11 tributary unit into an STM-1/VC-3 or TUG-3 from STM-1/VC-4
  
• Supports 28 T1 streams M13 multiplexed into a serial DS3
  
• Supports 21 E1 streams M13 multiplexed into a serial DS3 (compliant with ITU-T G.747)
  
• 28 T1 Streams M13 Multiplexed into a DS3 and DS3 is asynchronously mapped into STS-1
  
• 21 E1 Streams M13 Multiplexed into a DS3 (ITU-T G.747) and DS3 is asynchronously mapped into STS-1
  
• Supports 21 E1 mapped as Asynchronous VT2 into an STS-1 SPE or TU-12 tributary units into STM-1/VC-3 or TUG-3 from a STM-1/VC-4
  
• Supports TU cross-mapping function TU-12/VC-11/T1
  
• Supports mixed mapping of VT-G/VT1.5 and VT-G/VT2
  
• Supports mixed mapping of TUG-2/TU-11 and TUG-2/TU-12
  
• 28 VT1.5/TU-11 or 21 VT-2/TU-12 tributaries can be passed as transparent between SONET/SDH Telecom Bus on the line side and Clock and Data on the system side
  
• Supports Unframed T1/E1 signals
  
• Supports DS1/E1 Performance Monitoring in both Egress and Ingress direction
  
• VC-11/VC-12 Tandem Connection Monitoring support
  
• Complies with the Category I Intrinsic Jitter Requirements for DS1 signals being de-mapped from SONET, per Telcordia GR-253-CORE
  
• Complies with the "Mapping Jitter Generation Specification" for DS1 and E1 signals being de-mapped from SDH, per ITU-T G.783
  
• Complies with the "Combined Jitter Generation Specification" for DS1 and E1 signals being de-mapped from SDH, per ITU-T G.783
  
• Line and Facility Loop-backs
  
• Each of the 28 T1/E1 Channels includes a PRBS Generator and Receiver
  
• Each of the 28 VT-Mapper blocks are capable of generating BIP-2 and REI errors upon software command (for diagnostic purposes)
  
• The Transmit and Receive DS3 Framer blocks support both the M13(M23) and the C-bit Parity Framing formats
  
• Integrated 28 T1/E1/J1 Short-Haul Line Interface Units
  
• IEEE 1149.1 Standard Boundary Scan
  
• Low Power: 1.8V Power Supply for Core Logic; 3.3V Power Supply for I/O
  
• General Purpose Microprocessor Interface
  
• Pb-Free, RoHS Compliant Versions Offered

• Channelized and Unchannelized DS3 applications
  
• T1/E1 Terminals
  
• SONET/SDH ADM