|Information||Multi-Channel Line Interface Unit (LIU) Family Desynchronizer and Jitter Attenuator with RÂ³ Technologyâ„¢|
|Temperature Range (°C)||Ind.|
|# of Channels||12|
|Data Rate(s)||DS3, E3, STS-1|
|Op Pwr Sup/Max Cur||3V ±5%|
Recognized for an already robust series of physical layer, access and metro products, Exar extends its capabilities by adding to the industry's first monolithic desynchronization solution for mapping/demapping from SONET/SDH (synchronous) to DS3/E3 (asynchronous), R3 TechnologyTM.
Exar's R3 TechnologyTM was first introduced in 2002 as a breakthrough capability delivering key benefits to customers designing interface cards. Devices utilizing the technology are Reconfigurable with integrated clock synthesizer supporting DS3/E3/STS-1 clock rates from a single clock source. This capability enables customers to build one board with a single bill-of-materials, and gives them the agility to quickly respond and reconfigure devices for compressed design cycles. In addition, the series employs Relayless Redundancy eliminating the need for external relays for 1:1 and 1+1 applications by establishing a back-up channel that can be brought on-line in the event of failure.
The first T3/E3/STS-1 products to offer R3 TechnologyTM are the XRT75R03D (three) and XRT75R12D (twelve) Previously, Exar has offered this capability only on its T1/E1 LIU products. Now customers doing T3/E3 designs can take advantage of this unique technology saving time and cost in implementing redundancy as well as supporting global standards for Telecom.
The XRT75Rxx series has an independent receiver, transmitter and jitter attenuator in a single 52-pin TQFP package. It supports E3 (34.368.Mbps), DS3 (44.736Mbps) and STS-1 (51.84 Mbps) operations, has a differential receiver that provides a high noise interference margins -- capable of receiving data from cables of over 1,000 feet, or up to 12dB of cable attenuation. The device has an onboard Pseudo Random Binary Sequence (PRBS) generator and detector that can insert and detect single bit errors. This function is often used for diagnostic purposes. In addition, Exar adds desynchronization capability in its XRT75RxxD family.
What is Clock Desynchronization?
The process of mapping and subsequent de-mapping of DS3/E3 signals into SONET introduces excessive jitter and timing irregularities. Examples of jitter sources include mapping jitter, caused by bit justification, or stuffing, and pointer jitter, the outcome of frequency mismatches between networks that causes pointer movement. Current desynchronizing solutions use both a very narrow-bandwidth crystal oscillator based Phase Locked Loop (PLL) referred to as a Voltage Control Oscillator (VCXO), and a deep FIFO for each data rate and channel. For multi-channel/multi-rate applications, chip requirements can rise at exponential levels driven by the number of supported rates and channels. Enter Exar's solution; it uses only one highly integrated programmable PLL, now each channel can support multi-rate (DS3, E3 or STS-1) operations. Here jitter/timing irregularities are removed, and then desynchronized to provide a smooth GR-253-CORE specification-compliant clock signal. Once this operation is complete the signal is suitable for retransmission and returned to the data stream.
The receiver, transmitter, and jitter attenuator all meet Bellcore GR-499 CORE requirements. Also, the transmitter meets the GR-253 CORE and ANSI T1.102 specifications, and it includes a duty cycle correction PLL. The device meets jitter and wander specifications described in the T1.105.03b, and ETSI TBR-24, and is compliant with jitter transfer templates outlined in ITU G.751, G.752 and G.755.
- On-Chip Clock and Data Recovery Circuit for High-Input Jitter Tolerance
- On-Chip B3ZS/HDB3 Encoder/Decoder Can be Disabled or Enabled
- Able to receive data over 1000 feet of cable with up to 12 dB of cable attenuation
- Tri-state Transmit Output Capability for Redundancy Applications
- Transmitter Can be Turned On or Off
- Jitter Attenuator Can be Selected in Receive or Transmit Paths
- Selectable FIFO Size of 16 or 32 Bits
- Five Wire Serial Microprocessor for Control and Configuration
- Supports Optional Internal Transmit Driver Monitoring
- Reconfigurable relayless redundancy
- Pb-Free, RoHS Compliant Versions Offered
- E3/DS3 Access Equipment
- STS-1-SPE to DS# Mapper
- Digital Cross Connect Systems
- CSU/DSC Equipment
- Fiber Optic Terminals
Documentation & Design Tools
|Application Notes||TAN-200, MaxLinear APIs - OS Portability||1.0.0||August 2007||88.5 KB|
|Application Notes||TAN-075, DS-3/E3 LIU Layout Recommendations||1.0.0||February 2007||29.8 KB|
|Application Notes||TAN-067, R3 Technology For T/E Carrier Redundancy Applications||1.0.0||April 2004||203.4 KB|
|Schematics & Design Files||Schematic||1.0.0||January 2004||172.2 KB|
Quality & RoHS
Parts & Purchasing
|Part Number||Pkg Code||Min Temp||Max Temp||Status||Suggested Replacement||PDN|
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.
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