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Overview
Information | UART with 16-Byte FIFOs |
---|---|
Data Bus Interface | Intel |
# of Channels | 1 |
Max Data Rate 5V (Mbps) | 1.5 |
Max Data Rate 3.3V (Mbps) | 0.5 |
Max Data Rate 2.5V (Mbps) | na |
Max Data Rate 1.8V (Mbps) | na |
Tx FIFO (Bytes) | 16 |
Rx FIFO (Bytes) | 16 |
Auto Flow Control | |
Auto RS-485 Half-Duplex Control | |
Multidrop (9-bit) Mode | |
Fractional Baud Rate Generator | |
Power Down Mode | ✔ |
Supply Voltage Range VCC (V) | 2.97 to 5.5 |
Auto RTS/CTS | |
Package | TQFP-48 |
FIFO Level Counters | |
Selectable/ Programable Trigger Levels | S |
IrDA Sup | |
5V Tolerant Inputs | |
Max UART/GPIO Input Voltage (V) | VCC |
Max UART/GPIO Output Voltage (V) | VCC |
Temperature Range (°C) | -40 to 85 |
The ST16C1550, ST16C1551 series (here on denoted as the 155X) is a universal asynchronous receiver and transmitter (UART). The 155X is an improved version of the SSI 73M1550 and SSI 73M2550 UART with higher operating speed and lower access time. The 155X provides enhanced UART functions with 16 byte FIFOs, a modem control interface, independent programmable baud rate generators with clock rates to 1.5 Mbps.
Onboard status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by external software to meetspecific user requirements. An internal loopback capability allows onboard diagnostics. The 155X is available in a 28-pin PLCC/plastic-DIP, 48-pin TQFP packages.
The Baud rate generator can be configured for either crystal or external clock input with the exception of the 28 pin 1551 package.
An external clock must be provided for the 28 pin 1551 package. Each package type, with the exception of the 28 pin 1550, provides a buffered reset output that can be controlled through user software. DMA monitor signals TXRDY/RXRDY are not available at the 155X I/O pins but these signals are accessible through ISR register bits 4-5. Except as listed above, each package version has the same features. The 155X is functionally compatible with the 16C550. The 155X is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements.
- Pin and functionally compatible to SSI 73M1550/2550 Software compatible to INS8250, NS16C550
- 1.5 Mbps transmit/receive operation (24Mhz Max.) with programmable clock control
- 16 byte transmit FIFO
- 16 byte receive FIFO with error flags
- Four independently selectable Transmit and Receive FIFO interrupt trigger levels
- Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD)
- Programmable character lengths (5, 6, 7, 8) with Even, odd, or no parity
- Crystal or external clock input (except 28 pin ST16C1551)
- Provides enhanced 16C550 features for power down and software controllable reset output
- 460.8 Kbps transmit/receive operation with 7.3728 MHz crystal or external clock source
- Pb-Free, RoHS Compliant Versions Offered
- Battery Operated Electronics
- Internet Appliances
- Handheld Terminal
- Personal Digital Assistants
- Cellular Phones DataPort
Documentation & Design Tools
Type | Title | Version | Date | File Size |
---|---|---|---|---|
Data Sheets | ST16C1550/51 2.97V to 5.5V UART with 16-Byte FIFO | 4.2.1 | August 2005 | 741.4 KB |
Application Notes | DAN-108, UART Crystal Oscillator Design Guide | 1.0.0 | March 2000 | 218.1 KB |
Application Notes | DAN-107, Interfacing 16Cxxx UARTs to a CPU | 1.0.0 | August 1999 | 32.4 KB |
Application Notes | General UART Application Note | 1.0.0 | December 1996 | 39.8 KB |
Application Notes | AN-1450/AN-1550, ST16C1450 and ST16C1550 Application Example | 1.0.0 | December 1996 | 43.3 KB |
Product Brochures | Interface Brochure | November 2023 | 3.7 MB |
Quality & RoHS
Part Number | RoHS | Exempt | RoHS | Halogen Free | REACH | TSCA | MSL Rating / Peak Reflow | Package |
---|---|---|---|---|---|---|---|
ST16C1550CQ48-F | N | Y | Y | Y | Y | L3 / 260ᵒC | TQFP48 |
ST16C1550IQ48-F | N | Y | Y | Y | Y | L3 / 260ᵒC | TQFP48 |
ST16C1550CQ48TR-F | N | Y | Y | Y | Y | L3 / 260ᵒC | TQFP48 |
ST16C1550CJ28-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC28 |
ST16C1550IJ28-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC28 |
ST16C1550CJ28TR-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC28 |
Click on the links above to download the Certificate of Non-Use of Hazardous Substances.
Parts & Purchasing
Part Number | Pkg Code | Min Temp | Max Temp | Status | Suggested Replacement | Buy Now | Order Samples | PDN |
---|---|---|---|---|---|---|---|---|
ST16C1550CJ28-F | PLCC28 | 0 | 70 | OBS | ST16C1550CQ48-F | |||
ST16C1550CJ28TR-F | PLCC28 | 0 | 70 | OBS | ST16C1550CQ48TR-F | |||
ST16C1550CQ48-F | TQFP48 | 0 | 70 | Active | Order | |||
ST16C1550CQ48TR-F | TQFP48 | -40 | 85 | Active | Order | |||
ST16C1550IJ28-F | PLCC28 | -40 | 85 | OBS | ST16C1550IQ48-F | |||
ST16C1550IJ28TR-F | PLCC28 | -40 | 85 | OBS | ST16C1550IJ28-F | |||
ST16C1550IQ48-F | TQFP48 | -40 | 85 | Active | Order | |||
ST16C1550IQ48TR-F | TQFP48 | -40 | 85 | OBS | ST16C1550IQ48-F |
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.
Packaging
Notifications
FAQs & Support
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Please check that all the following conditions are satisfied first.
- no interrupts pending (ISR bit-0 = 1)
- modem inputs are not toggling (MSR bits 0-3 = 0)
- RX input pin is idling HIGH • divisor (the value in DLL register) is non-zero
- TX and RX FIFOs are empty
Be sure sleep mode bit has been set to 1. If there are multiple UART channels, the sleep conditions must be true for all channels.
See more on Sleep Mode in AN204 UART Sleep Mode.
Yes. Note: some devices do have powersave mode. If UART goes into powersave mode, then the registers are not accessible.
See more on Sleep Mode in AN204 UART Sleep Mode.
Read LSR register to check whether the UART receives the data or not.
- If LSR value is 0x60, it means that either UART receiver FIFO doesn’t receive the data or the data in receiver FIFO has been read out before the read of LSR.
- If LSR value is 0x00, it means data is still in the THR (clock doesn’t oscillate to transmit data).
- If LSR value is 0xFF, it means either UART is in powersave mode or UART is powered off. For those devices with powersave mode, be sure that UARTS are not in powersave mode.
See more on Sleep Mode in AN204 UART Sleep Mode.
- Check whether the register set can be accessed.
- Check whether the crystal is oscillating fully.
- Check whether the data can be transmitted in internal loopback mode.
See more on Sleep Mode in AN204 UART Sleep Mode.