Overview
Information | Dual Universal Asynchronous Receiver and Transmitter (UART) |
---|---|
Data Bus Interface | Intel |
# of Channels | 2 |
Max Data Rate 5V (Mbps) | 4 |
Max Data Rate 3.3V (Mbps) | 1.8 |
Max Data Rate 2.5V (Mbps) | na |
Max Data Rate 1.8V (Mbps) | na |
Tx FIFO (Bytes) | 16 |
Rx FIFO (Bytes) | 16 |
Auto Flow Control | |
Auto RS-485 Half-Duplex Control | |
Multidrop (9-bit) Mode | |
Fractional Baud Rate Generator | |
Power Down Mode | |
Supply Voltage Range VCC (V) | 2.97 to 5.5 |
Auto RTS/CTS | |
Package | PLCC-44 |
FIFO Level Counters | |
Selectable/ Programable Trigger Levels | S |
IrDA Sup | |
5V Tolerant Inputs | ✔ |
Max UART/GPIO Input Voltage (V) | 5.5 |
Max UART/GPIO Output Voltage (V) | VCC |
Temperature Range (°C) | -40 to 85 |
The ST16C2552 (2552) is a dual universal asynchronous receiver and transmitter (UART). The ST16C2552 is an improved version of the PC16552 UART. The 2552 provides enhanced UART functions with 16 byte FIFOs, a modem control interface, and data rates up to 4 Mbps. Onboard status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by external software to meet specific user requirements. Indepedendent programmable baud rate generators are provided to select transmit and receive clock rates from 50 Bps to 4 Mbps. The baud rate generator can be configured for either crystal or external clock input. An internal loopback capability allows onboard diagnostics. The 2552 provides block mode data transfers (DMA) through FIFO controls. DMA transfer monitoring is provided through the signals TXRDY# and RXRDY#. An Alternate Function Register provides the user with the ability to write the control registers for both UARTs concurrently. The 2552 is available in the 44-PLCC package.
- Pin-to-pin and functionally compatible to National PC16552
- Pin-to-pin Compatible to Exar’s XR16L2752 and XR16C2852
- 4 Mbps transmit/receive operation (64 MHz External Clock Frequency)
- 2 Independent UART Channels
- Register Set Compatible to 16C550
- 16 byte Transmit FIFO to reduce the bandwidth requirement of the external CPU
- 16 byte Receive FIFO with error tags to reduce the bandwidth requirement of the external CPU
- 4 selectable RX FIFO Trigger Levels
- Fixed Transmit FIFO interrupt trigger level
- Full Modem Interface (CTS#, RTS#, DSR#, DTR#, RI#, CD#)
- DMA operation and DMA monitoring via TXRDY# and RXRDY# pins
- UART internal register sections A & B may be written to concurrently
- Multi-Function output allows more package functions with few I/O pins
- Programmable character lengths (5, 6, 7, 8) with even, odd, or no parity
- Crystal oscillator or external clock input
- Industrial and commercial temperature ranges
- Pb-Free, RoHS Compliant Versions Offered
- Portable Appliances
- Telecommunication Network Routers
- Ethernet Network Routers
- Cellular Data Devices
- Factory Automation and Process Controls
Documentation & Design Tools
Type | Title | Version | Date | File Size |
---|---|---|---|---|
Data Sheets | ST16C2552 2.97V to 5.5V Dual UART with 16-Byte FIFO | 4.2.2 | September 2012 | 755 KB |
Application Notes | DAN-180, Use of MaxLinear’s ST16C2550 with Linux 2.4.X & 2.6.X OS, Phoenix Bios Version 4.0 Release 6.0 and Windows Operating Systems | 1.0.1 | October 2007 | 93.3 KB |
Application Notes | DAN-107, Interfacing 16Cxxx UARTs to a CPU | 1.0.0 | August 1999 | 32.4 KB |
Application Notes | General UART Application Note | 1.0.0 | December 1996 | 39.8 KB |
User Guides & Manuals | Evaluation Board User's Manual | 1.3.0 | August 2003 | 24.7 KB |
Product Brochures | Interface Brochure | R01 | June 2024 | 3.6 MB |
Schematics & Design Files | ISA Eval Board Schematic | 1.4.0 | August 2007 | 109 KB |
Quality & RoHS
Part Number | RoHS | Exempt | RoHS | Halogen Free | REACH | TSCA | MSL Rating / Peak Reflow | Package |
---|---|---|---|---|---|---|---|
ST16C2552CJ44-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC44 |
ST16C2552IJ44-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC44 |
ST16C2552CJ44TR-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC44 |
ST16C2552IJ44TR-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC44 |
Click on the links above to download the Certificate of Non-Use of Hazardous Substances.
Parts & Purchasing
Part Number | Pkg Code | Min Temp | Max Temp | Status | Buy Now | Order Samples |
---|---|---|---|---|---|---|
ST16C2552CJ44-F | PLCC44 | 0 | 70 | Active | Order | |
ST16C2552CJ44TR-F | PLCC44 | 0 | 70 | Active | Order | |
ST16C2552IJ44-F | PLCC44 | -40 | 85 | Active | Order | |
ST16C2552IJ44TR-F | PLCC44 | -40 | 85 | Active | Order |
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.
Packaging
Pkg Code | Details | Quantities | Dimensions |
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PLCC44 |
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Notifications
FAQs & Support
Search our list of FAQs for answers to common technical questions.
For material content, environmental, quality and reliability questions review the Quality tab or visit our Quality page.
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The Parts & Purchasing section of the product page shows the Status of all orderable part numbers for that product. Click Show obsolete parts, to see all EOL or OBS products.
Please check that all the following conditions are satisfied first.
- no interrupts pending (ISR bit-0 = 1)
- modem inputs are not toggling (MSR bits 0-3 = 0)
- RX input pin is idling HIGH • divisor (the value in DLL register) is non-zero
- TX and RX FIFOs are empty
Be sure sleep mode bit has been set to 1. If there are multiple UART channels, the sleep conditions must be true for all channels.
See more on Sleep Mode in AN204 UART Sleep Mode.
Yes. Note: some devices do have powersave mode. If UART goes into powersave mode, then the registers are not accessible.
See more on Sleep Mode in AN204 UART Sleep Mode.
Read LSR register to check whether the UART receives the data or not.
- If LSR value is 0x60, it means that either UART receiver FIFO doesn’t receive the data or the data in receiver FIFO has been read out before the read of LSR.
- If LSR value is 0x00, it means data is still in the THR (clock doesn’t oscillate to transmit data).
- If LSR value is 0xFF, it means either UART is in powersave mode or UART is powered off. For those devices with powersave mode, be sure that UARTS are not in powersave mode.
See more on Sleep Mode in AN204 UART Sleep Mode.
- Check whether the register set can be accessed.
- Check whether the crystal is oscillating fully.
- Check whether the data can be transmitted in internal loopback mode.
See more on Sleep Mode in AN204 UART Sleep Mode.