Overview
Information | UART With 16-Byte FIFOs |
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Data Bus Interface | Intel |
# of Channels | 1 |
Max Data Rate 5V (Mbps) | 1.5 |
Max Data Rate 3.3V (Mbps) | 1 |
Max Data Rate 2.5V (Mbps) | na |
Max Data Rate 1.8V (Mbps) | na |
Tx FIFO (Bytes) | 16 |
Rx FIFO (Bytes) | 16 |
Auto Flow Control | |
Auto RS-485 Half-Duplex Control | |
Multidrop (9-bit) Mode | |
Fractional Baud Rate Generator | |
Power Down Mode | |
Supply Voltage Range VCC (V) | 2.97 to 5.5 |
Auto RTS/CTS | |
Package | PLCC-44, TQFP-48 |
FIFO Level Counters | |
Selectable/ Programable Trigger Levels | S |
IrDA Sup | |
5V Tolerant Inputs | |
Max UART/GPIO Input Voltage (V) | VCC |
Max UART/GPIO Output Voltage (V) | VCC |
Temperature Range (°C) | -40 to 85 |
The ST16C550 is a universal asynchronous receiver and transmitter with 16-byte transmit and receive FIFO. A programmable baud rate generator is provided to select transmit and receive clock rates from 50bps to 1.5Mbps.
The ST16C550 is an improved version of the NS16C550 UART with higher operating speed and lower access time. The ST16C550 onboard status registers provides the error conditions, type and status of the transfer operation being performed. Included is complete MODEM control capability and a processor interrupt system that may be software tailored to the user’s requirements. The ST16C550 provides internal loop-back capability for onboard diagnostic testing.
The ST16C550 is available in 40-pin PDIP, 44-pin PLCC and 48-pin TQFP packages. It is fabricated in an advanced 0.6m CMOS process to achieve low drain power and high speed requirements.
- Pin-to-pin and functionally compatible to the industry standard 16C550
- 24MHz clock operation at 5V
- 16MHz clock operation at 3.3V
- 16-byte transmit FIFO
- 16-byte receive FIFO with error flags
- Full duplex operation
- Transmit and receive control
- Four selectable receive FIFO interrupt trigger levels
- Standard modem interface
- Compatible with ST16C450
- Low operating current (1.2mA typ.)
- Pb-Free, RoHS compliant versions offered
- Battery Operated Electronics
- Internet Appliances
- Handheld Terminal
- Personal Digital Assistants
- Cellular Phones DataPort
Documentation & Design Tools
Type | Title | Version | Date | File Size |
---|---|---|---|---|
Data Sheets | ST16C550 UART with 16-Byte FIFO’s | 5.0.1 | April 2005 | 241.1 KB |
Application Notes | DAN-132, ST16C550 vs. TL16C550C | 1.0.0 | June 2002 | 121.5 KB |
Application Notes | DAN-108, UART Crystal Oscillator Design Guide | 1.0.0 | March 2000 | 218.1 KB |
Application Notes | General UART Application Note | 1.0.0 | December 1996 | 39.8 KB |
Application Notes | AN-450/AN-550, ST16C450/550 Application Example | 1.0.0 | December 1996 | 44.2 KB |
User Guides & Manuals | Evaluation Board User's Manual | 1.1.0 | October 2003 | 14.3 KB |
Product Brochures | Interface Brochure | R01 | June 2024 | 3.6 MB |
Schematics & Design Files | ISA Eval Board Schematic | 1.4.0 | August 2007 | 77.6 KB |
Schematics & Design Files | ISA Eval Board Schematic | 1.2.0 | August 2007 | 81.4 KB |
Software: Drivers | Linux 2.4 | 1.0 | December 2009 | 907.6 KB |
Software: Drivers | Windows 95 & 98 | 1.0.0.0 | December 2009 | 105.2 KB |
Software: Drivers | Windows NT | 1.0.0.0 | December 2009 | 663.4 KB |
Quality & RoHS
Part Number | RoHS | Exempt | RoHS | Halogen Free | REACH | TSCA | MSL Rating / Peak Reflow | Package |
---|---|---|---|---|---|---|---|
ST16C550CQ48-F | N | Y | Y | Y | Y | L3 / 260ᵒC | TQFP48 |
ST16C550IQ48-F | N | Y | Y | Y | Y | L3 / 260ᵒC | TQFP48 |
ST16C550CQ48TR-F | N | Y | Y | Y | Y | L3 / 260ᵒC | TQFP48 |
ST16C550IQ48TR-F | N | Y | Y | Y | Y | L3 / 260ᵒC | TQFP48 |
ST16C550CJ44-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC44 |
ST16C550IJ44-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC44 |
ST16C550CJ44TR-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC44 |
Click on the links above to download the Certificate of Non-Use of Hazardous Substances.
Parts & Purchasing
Part Number | Pkg Code | Min Temp | Max Temp | Status | Suggested Replacement | Buy Now | Order Samples | PDN |
---|---|---|---|---|---|---|---|---|
ST16C550CJ44-F | PLCC44 | 0 | 70 | Active | Order | |||
ST16C550CJ44TR-F | PLCC44 | 0 | 70 | Active | Order | |||
ST16C550CP40 | PDIP40 | 0 | 70 | OBS | ST16C550CP40-F | |||
ST16C550CP40-F | PDIP40 | 0 | 70 | OBS | ST16C550CJ44-F , ST16C550CQ48-F | |||
ST16C550CQ48-F | TQFP48 | 0 | 70 | Active | Order | |||
ST16C550CQ48TR-F | TQFP48 | 0 | 70 | Active | Order | |||
ST16C550IJ44-F | PLCC44 | -40 | 85 | Active | Order | |||
ST16C550IJ44TR-F | PLCC44 | -40 | 85 | OBS | ST16C550IJ44-F | |||
ST16C550IP40 | PDIP40 | -40 | 85 | OBS | ST16C550IP40-F | |||
ST16C550IP40-F | PDIP40 | -40 | 85 | OBS | ST16C550IJ44-F , ST16C550IQ48-F | |||
ST16C550IQ48-F | TQFP48 | -40 | 85 | Active | Order | |||
ST16C550IQ48TR-F | TQFP48 | -40 | 85 | Active | Order |
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.
Packaging
Pkg Code | Details | Quantities | Dimensions |
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PDIP40 |
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PLCC44 |
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TQFP48 |
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Notifications
FAQs & Support
Search our list of FAQs for answers to common technical questions.
For material content, environmental, quality and reliability questions review the Quality tab or visit our Quality page.
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Please check that all the following conditions are satisfied first.
- no interrupts pending (ISR bit-0 = 1)
- modem inputs are not toggling (MSR bits 0-3 = 0)
- RX input pin is idling HIGH • divisor (the value in DLL register) is non-zero
- TX and RX FIFOs are empty
Be sure sleep mode bit has been set to 1. If there are multiple UART channels, the sleep conditions must be true for all channels.
See more on Sleep Mode in AN204 UART Sleep Mode.
Yes. Note: some devices do have powersave mode. If UART goes into powersave mode, then the registers are not accessible.
See more on Sleep Mode in AN204 UART Sleep Mode.
Read LSR register to check whether the UART receives the data or not.
- If LSR value is 0x60, it means that either UART receiver FIFO doesn’t receive the data or the data in receiver FIFO has been read out before the read of LSR.
- If LSR value is 0x00, it means data is still in the THR (clock doesn’t oscillate to transmit data).
- If LSR value is 0xFF, it means either UART is in powersave mode or UART is powered off. For those devices with powersave mode, be sure that UARTS are not in powersave mode.
See more on Sleep Mode in AN204 UART Sleep Mode.
- Check whether the register set can be accessed.
- Check whether the crystal is oscillating fully.
- Check whether the data can be transmitted in internal loopback mode.
See more on Sleep Mode in AN204 UART Sleep Mode.