XR16C2852

Dual UART with TX and RX FIFO Counters, 128-Byte FIFO and Automatic RS-485 Half Duplex Control
Data Sheets EOL (End of Life)

Overview

Information Dual UART with TX and RX FIFO Counters, 128-Byte FIFO and Automatic RS-485 Half Duplex Control
Data Bus Interface Intel
# of Channels 2
Max Data Rate 5V (Mbps) 3.125
Max Data Rate 3.3V (Mbps) 2
Max Data Rate 2.5V (Mbps) na
Max Data Rate 1.8V (Mbps) na
Tx FIFO (Bytes) 128
Rx FIFO (Bytes) 128
Auto Flow Control ✔
Auto RS-485 Half-Duplex Control ✔
Multidrop (9-bit) Mode
Fractional Baud Rate Generator
Power Down Mode ✔
Supply Voltage Range VCC (V) 2.97 to 5.5
Auto RTS/CTS ✔
Package PLCC-44
FIFO Level Counters ✔
Selectable/ Programable Trigger Levels P
IrDA Sup ✔
5V Tolerant Inputs ✔
Max UART/GPIO Input Voltage (V) 5.5
Max UART/GPIO Output Voltage (V) VCC
Temperature Range (°C) -40 to 85
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The XR16C2852 (2852) is a dual universal asynchronous receiver and transmitter (UART). The 2852 provides enhanced UART functions with 128 byte FIFO, automatic RS-485 half duplex control, a modem control interface, and data rates up to 1.5 Mbps. Onboard status registers provide the user with error indications and operational status. An alternate function register supports concurrent write to UART A and B. System interrupts and modem control features may be tailored by external software to meet specific user requirements.

An internal loopback capability allows onboard diagnostics. Independent programmable baud rate generators are provided to select transmit and receive clock rates up to 1.5 Mbps. The baud rate generator can be configured for either crystal or external clock input. The 2852 is available in a 44-pin PLCC package and functionally compatible with the ST16C2552. The 2852 is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements.


  • Pin and functionally compatible to ST16C2552, and National PC16552/NS16C552
  • Independent channel A/B control
  • Up to 1.5 Mbps data rate operation
  • 128 byte transmit FIFO to reduce CPU bandwidth requirement
  • 128 byte receive FIFO with error flags to reduce CPU bandwdth requirement
  • Programmable transmit and receive FIFO trigger level from 0 to 127
  • Automatic RTS/CTS flow control with hysteresis
  • Automatic software flow control
  • Automatic RS485 half duplex direction control on -RTS pin
  • Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD, and software controllable line break)
  • Infrared (IrDA ver 1.0) transmit and receive data encoder/decoder
  • Device identification and revision
  • Standard 460.8 Kbps transmit/receive data rate with 7.3728 MHz crystal or external clock source
  • +5V or 3.3V operation
  • Industrial and commercial temperature grades
  • 44-pin PLCC package
  • Pb-Free, RoHS Compliant Versions Offered

  • Portable Appliances
  • Telecommunication Network Routers
  • Ethernet Network Routers
  • Cellular Data Devices
  • Factory Automation and Process Controls

Documentation & Design Tools

All Types Data Sheets Application Notes Schematics & Design Files Product Briefs & Brochures Software & Utilities Design Tools & Simulation User Guides & Manuals
Type Title Version Date File Size
Data Sheets XR16C2852 2.97V to 5.5V Dual UART with 128-Byte FIFOS 2.1.1 February 2005 853.5 KB
Application Notes DAN-190, MaxLinear UARTs in RS-485 Applications R01 July 2023 2.4 MB
Application Notes AN-204, UART Sleep Mode 1.0.0 June 2010 515.8 KB
Application Notes DAN-162, Migrating from XR16C2852 to XR16L2752 1.0.0 August 2002 17.2 KB
Application Notes DAN-108, UART Crystal Oscillator Design Guide 1.0.0 March 2000 218.1 KB
Application Notes DAN-107, Interfacing 16Cxxx UARTs to a CPU 1.0.0 August 1999 32.4 KB
User Guides & Manuals Evaluation Board User's Manual 1.3.0 August 2003 24.7 KB
Schematics & Design Files ISA Eval Board Schematic 1.4.0 August 2007 109 KB
Schematics & Design Files PCI Eval Board Schematic 1.1.0 July 2007 167.8 KB
Software: Drivers Linux 2.6.13 1.0.0 December 2009 10.8 KB
Software: Drivers Linux 2.6.18 1.0.0 December 2009 12.1 KB
Software: Drivers Windows XP & 2000 1.3.0.0 December 2009 61 KB
Product Brochures Serial Transceivers & Bridges Brochure R03 May 2025 3.6 MB
Simulation Models
Package Type Vcc Temp Mode Version File
PLCC 3.3V Commercial Intel 1
PLCC 5V Commercial Intel 1
PLCC 3.3V Industrial Intel 1
PLCC 5V Industrial Intel 1
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Quality & RoHS

Part Number RoHS | Exempt RoHS Halogen Free REACH TSCA MSL Rating / Peak Reflow Package
XR16C2852CJ-F N Y Y Y Y L1 / 260ᵒC PLCC44
XR16C2852IJ-F N Y Y Y Y L1 / 260ᵒC PLCC44
XR16C2852IJTR-F N Y Y Y Y L1 / 260ᵒC PLCC44

Click on the links above to download the Certificate of Non-Use of Hazardous Substances.

Additional Quality Documentation may be available, please Contact Support.

Parts & Purchasing

Part Number Pkg Code Min Temp Max Temp Status Suggested Replacement Buy Now PDN
XR16C2852CJ-F PLCC44 0 70 EOL
XR16C2852CJTR-F PLCC44 0 70 OBS XR16C2852CJ-F
XR16C2852IJ-F PLCC44 -40 85 EOL
XR16C2852IJTR-F PLCC44 -40 85 EOL
Show obsolete parts
Part Status Legend
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.

Packaging

Pkg Code Details Quantities Dimensions
PLCC44
  • JEDEC Reference: MS-018
  • MSL Pb-Free: L1 @ 260ºC
  • MSL SnPb Eutectic: n/a
  • ThetaJA: 38.0ºC/W
  • Bulk Pack Style: Tube
  • Quantity per Bulk Pack: 27
  • Quantity per Reel: 500
  • Quantity per Tube: 27
  • Quantity per Tray: n/a
  • Reel Size (Dia. x Width x Pitch): 330 x 32 x 24
  • Tape & Reel Unit Orientation: Pin 1 at sprocket hole.
  • Dimensions: mm
  • Length: 16.585
  • Width: 16.585
  • Thickness: 4.57
  • Lead Pitch: 1.27

Notifications

Distribution Date Description File
01/08/2025 Product Discontinuation Notice
07/17/2023 In 2023, MaxLinear will be converting all shipping labels for the parts noted from an EXAR format to MaxLinear’s label. During this transition customers may receive either label. This change affects only shipping and packing labels. This change will not affect the part number, part marking, manufacturing process or manufacturing sites. Only work in progress material will be converted. Existing inventory from MaxLinear’s warehouse, channel sales, distributor, and such, will not be converted. Hence, customers may experience receiving mixed shipments with both Exar and MaxLinear labels for some period until existing inventory of old labels is eventually cleared out. Situation is product to product with no predictable way to determine when all old labels will be exhausted. No change to product form, fit, function and reliability. ADDENDUM A: Fixed MBB label logo for DX204001 to MaxLinear logo. ADDENDUM B: Replaced ‘All other affected products outer box label’ with clearer pictures. Corrected Date Issued (from original PCN) issue date +90 days to August 30, 2023.
06/01/2023 In 2023, MaxLinear will be converting all shipping labels for the parts noted from an EXAR format to MaxLinear’s label. During this transition customers may receive either label. This change affects only shipping and packing labels. This change will not affect the part number, part marking, manufacturing process or manufacturing sites. Only work in progress material will be converted. Existing inventory from MaxLinear’s warehouse, channel sales, distributor, and such, will not be converted. Hence, customers may experience receiving mixed shipments with both Exar and MaxLinear labels for some period until existing inventory of old labels is eventually cleared out. Situation is product to product with no predictable way to determine when all old labels will be exhausted. No change to product form, fit, function and reliability.
06/01/2023 In 2023, MaxLinear will be converting all shipping labels for the parts noted from an EXAR format to MaxLinear’s label. During this transition customers may receive either label. This change affects only shipping and packing labels. This change will not affect the part number, part marking, manufacturing process or manufacturing sites. Only work in progress material will be converted. Existing inventory from MaxLinear’s warehouse, channel sales, distributor, and such, will not be converted. Hence, customers may experience receiving mixed shipments with both Exar and MaxLinear labels for some period until existing inventory of old labels is eventually cleared out. Situation is product to product with no predictable way to determine when all old labels will be exhausted. No change to product form, fit, function and reliability. ADDENDUM: Fixed MBB label logo for DX204001 to MaxLinear logo.
08/21/2020 MaxLinear has qualified Greatek, Taiwan, as an alternate assembly site for the products listed above. There is no change to datasheet form, fit, function.
07/11/2017 Product Discontinuation Notification
11/05/2015 Updated information subsequent to original published PCN 13-0834-03 on 04/02/2014. ASE Malaysia as alternate assembly site Addition of qualified alternate assembly site of 28, 44, 68L PLCC packaged products.
04/02/2014 Qualification of ASE Malaysia for assembly of 28, 44, 68L PLCC packaged products. Alternate assembly site.
10/17/2012 Exar has qualified Millennium Microtech/Thailand as an alternate assembly supplier for 28, 44 and 68 lead PLCC packages in addition to the existing supplier, Unisem/Indonesia. Capacity enhancement

FAQs & Support

Search our list of FAQs for answers to common technical questions.
For material content, environmental, quality and reliability questions review the Quality tab or visit our Quality page.
For ordering information and general customer service visit our Contact Us page.

Submit a Technical Support Question As a New Question

LSR bit-6 is a superset of LSR bit-5. The transmitter consists of a TX FIFO (or THR only when FIFOs are not enabled) and a Transmit Shift Register (TSR). When LSR bit-5 is set, it indicates that the TX FIFO (or THR) is empty, however there may be data in the TSR. When LSR bit-6 is set, it indicates that the transmitter (TX FIFO + TSR) is completely empty.

You can tell by reading LSR bit-5 or bit-6. If they are '0', then the transmit interrupt was generated by the trigger level. If they are '1', then the transmit interrupt was generated by the TX FIFO becoming empty. For enhanced UARTs, you can just read the FIFO level counters.

An RX Data Ready interrupt is generated when the number of bytes in the RX FIFO has reached the RX trigger level. An RX Data Timeout interrupt is generated when the RX input has been idle for 4 character + 12 bits time.

For some UARTs, the RX Data Timeout interrupt has a higher priority and in others, the RX Data Ready interrupt has a higher priority. See the interrupt priority section of the datasheet.

The UART requires a clock and a valid baud rate in order to transmit and receive data. Check that there is a clock signal on the XTAL1 input pin. Also, valid divisors need to be written into the DLL and DLM registers. Most UARTs have random (invalid) values upon power-up.

For most UARTs, the interrupt is generated when the data is ready to be read from the RX FIFO. The are some UARTs that generate the interrupt when the character with the error is received. There are some UARTs that have a register bit to select whether the LSR interrupt is generated immediately or delayed until it is ready to be read.

The UART will enter the sleep mode if the following conditions have been satisfied for all channels:
 
-Sleep Mode is enabled
-No interrupts are pending
-TX and RX FIFOs are empty
-RX input pin is idling HIGH (LOW in IR mode)
-Valid values in DLL and DLM registers
-Modem input pins are idle (MSR bits 3-0=0x0)
 
See AN204, UART Sleep Mode for more information on UART Sleep Mode

The UART will wake-up from sleep mode by any of the following conditions on any channel:
 
-Sleep mode is disabled
-Interrupt is generated
-Data is written into THR
-There is activity on the RX input pin
-There is activity on the modem input pins
 
If the sleep mode is still enabled and all wake-up conditions have been cleared, it will return to the sleep mode.
 
See AN204, UART Sleep Mode for more information on UART Sleep Mode 

There will be no activity on the XTAL2 output.
 
See AN204, UART Sleep Mode for more information on UART Sleep Mode 

For any UART that has the wake-up indicator interrupt, an interrupt will be generated when the UART wakes up even if no other interrupts are enabled.
 
See AN204, UART Sleep Mode for more information on UART Sleep Mode 

No, Auto RTS and Auto CTS are independent. Auto RTS is toggled by the UART receiver. Auto CTS is monitored by the UART Transmitter.

No, Auto RTS and Auto CTS will work normally without the interrupts enabled.

No, software flow control characters are not loaded into the RX FIFO.

Since 2-character software flow control requires that 2 consecutive flow control characters match before data transmission is stopped or resumes, there is less of a chance that data transmission is stopped because one data byte matched a control character.

Auto RS485 Half-Duplex Control feature overrides the Auto RTS flow control feature if both features use the RTS# output pin. Both features can only be used simultaneously if the Auto RS485 control output is not the RTS# output. For some UARTs, the Auto RS485 control output is not the RTS# output.

Most UARTs use RTS#, however the XR16C850 and XR16C864 use the OP1# output as the Auto RS485 control output. In addition to using the RTS# output as the Auto RS485 control output, the XR16L784, XR16L788 and XR16V798 can use the DTR# output as the Auto RS485 control output.

The polarity of the RS485 control output varies from one UART to another. For some UARTs, an inverter may be required. Some of the newer UARTs have register bits that can change that polarity of the RS485 control output.

In the normal mode, the TX interrupt is generated when the TX FIFO is empty, and there may still be data in the Transmit Shift Register. In the RS485 mode, the TX interrupt is generated when the TX FIFO and the TSR register are both empty.

It is recommended that the FIFO counters at the Scratchpad Register location be used. When transmitting or receiving data, writing to the LCR register could result in transmit and/or receive data errors.

Due to the dynamic nature of the FIFO counters, it is recommended that the FIFO counter registers be read until consecutive reads return the same value.

All of the UARTs that have the IR mode supports up to 115.2Kbps as specified in IrDA 1.0. The newer I2C/SPI UARTs can support up to 1.152Mbps as specified in IrDA 1.1.

For external clock frequencies above 24MHz at the XTAL1 input, a 2K pull-up may be necessary to improve the rise times if there are data transmission errors.

Yes, you can daisy-chain it like that, but only up to 2 times (3 UARTs total in the daisy-chain). The UARTs should be as close as possible.

No, it just has to meet the minimum high and low pulse widths.

Yes, if you are using a UART with a fractional baud rate generator. This provides a divisor feature with a granularity of 1/16, allowing for any baud rate to be generated by any clock frequency, standard or non-standard. Click on the parametric search button of the product family page and find the Fractional Baud Rate Generator column which tells which products have this feature.

They crystal oscillator circuitry is recommended for fundamental frequency crystals only. The maximum frequency for crystals with fundamental frequencies is typically 24MHz. Above that frequency, crystals operate at higher harmonics, which will not work with the recommended crystal oscillator circuitry.

No. It is only required for transmitting and receiving data.

The -F suffix indicates ROHS / Green compliance:
https://www.exar.com/quality-assurance-and-reliability/lead-free-program

Visit the product page for the part you are interested in.  The part's status is listed in the Parts & Purchasing section.  You can also view Product Lifecycle and Obsolescence Information including PDNs (Product Discontinuation Notifications).

 

To visit a product page, type the part into the search window on the top of the MaxLinear website.

 

In this example, we searched for XR33180.  Visit the product page by clicking the part number or visit the orderable parts list by clicking "Orderable Parts". 

 

XR33180 Search Result

 

  

The Parts & Purchasing section of the product page shows the Status of all orderable part numbers for that product.  Click Show obsolete parts, to see all EOL or OBS products.

 

 Show Obsolete parts to expand the list

It depends on the baud rate. For example, for a start bit, 8 data bits, no stop bit and 1 stop bit, the maximum baud rate deviation is 4.76%. For more information, see https://www.exar.com/appnote/dan108.pdf

Please check that all the following conditions are satisfied first.

 

  • no interrupts pending (ISR bit-0 = 1)
  • modem inputs are not toggling (MSR bits 0-3 = 0)
  • RX input pin is idling HIGH • divisor (the value in DLL register) is non-zero
  • TX and RX FIFOs are empty

 

Be sure sleep mode bit has been set to 1. If there are multiple UART channels, the sleep conditions must be true for all channels.

 

See more on Sleep Mode in AN204 UART Sleep Mode.

Yes. Note: some devices do have powersave mode. If UART goes into powersave mode, then the registers are not accessible.

 

See more on Sleep Mode in AN204 UART Sleep Mode.

Read LSR register to check whether the UART receives the data or not.

 

  • If LSR value is 0x60, it means that either UART receiver FIFO doesn’t receive the data or the data in receiver FIFO has been read out before the read of LSR.
  • If LSR value is 0x00, it means data is still in the THR (clock doesn’t oscillate to transmit data).
  • If LSR value is 0xFF, it means either UART is in powersave mode or UART is powered off. For those devices with powersave mode, be sure that UARTS are not in powersave mode.

 

 

See more on Sleep Mode in AN204 UART Sleep Mode.

 

  • Check whether the register set can be accessed.
  • Check whether the crystal is oscillating fully.
  • Check whether the data can be transmitted in internal loopback mode.

 

 

See more on Sleep Mode in AN204 UART Sleep Mode.

Videos

English Chinese

MxL UARTs Auto RS-485 Direction Control

This video describes how the automatic RS-485 half-duplex direction control feature in MaxLinear UARTs reduces driver development and frees up CPU/MCU loading. This feature eliminates the need to monitor the status of the UART’s transmit shift register and automatically switches MaxLinear RS-485 transceivers from the transmit mode to the receive mode. This video summarizes the content in application note DAN-190. 

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