XR16C2852

Documentation

• Datasheet

  • XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

• Application Notes

  • DAN-108, UART Crystal Oscillator Design Guide
  • DAN-107, Interfacing 16Cxxx UARTs to a CPU
  • DAN-162, Migrating from XR16C2852 to XR16L2752
  • DAN-190, Exar UARTs in RS-485 Applications
  • AN-204, UART Sleep Mode

• Manuals

  • Evaluation Board User's Manual

• Schematics

  • PCI Eval Board Schematic
  • ISA Eval Board Schematic

• Product Brochure

  • Interface Brochure

Application

• Portable Appliances
  
• Telecommunication Network Routers
  
• Ethernet Network Routers
  
• Cellular Data Devices
  
• Factory Automation and Process Controls

Packaging

Parts & Purchasing

Quality Documents

Frequently Asked Questions

How can I find out if the status of a part number is EOL / obsolete or active?

The best way to determine this is to go to exar.com and type the part into the search function. At or near the top of the results you should see something that looks like

 

 

In this example, we looked for XRA1201. When you hover over it, it will turn grey and you can click anywhere in the grey box. This brings you to the product page. For example:

 

 

Click on Parts & Purchasing, highlighted in yellow above. The screen changes to:

 

Notice the status column and the “Show obsolete parts” link:

 

A legend tells you the definition of the different statuses. Click on the “Show obsolete parts” link to see EOL or OBS part numbers along with the Active part numbers:

 

 

Another method to find out if a part is OBS or EOL is to click on SUPPORT:

 

And then Product Change Notifications

 

 

Type the part into the search, and click on one of the part numbers from the drop down menu. Then you can look for the Product Discontinuation Notice, which generally is at the top of the list, for example:

 

 

If you see this, it tells you that this particular orderable part has been discontinued and when the last order date is, or was. If you click on the file, then you can view the notice we sent about this if you purchased the part in the recent past. It may also advise of a replacement part. When an orderable part first becomes discontinued, Product Discontinuation Notices are sent are sent to those who have purchased the parts in the recent past, if purchased directly, with a dated opportunity to place a last order.

Can I use the XTAL2 output of one UART and feed that to the XTAL1 input of another UART?

Yes, you can daisy-chain it like that, but only up to 2 times (3 UARTs total in the daisy-chain). The UARTs should be as close as possible.

When using an external clock for the UART, does the duty cycle of the clock have to be 50-50%?

No, it just has to meet the minimum high and low pulse widths.

What is the maximum deviation that the UART can tolerate without receiving errors?

It depends on the baud rate. For example, for a start bit, 8 data bits, no stop bit and 1 stop bit, the maximum baud rate deviation is 4.76%. For more information, see https://www.exar.com/appnote/dan108.pdf

When is a 2K pull-up on the XTAL2 output of the UART recommended?

For external clock frequencies above 24MHz at the XTAL1 input, a 2K pull-up may be necessary to improve the rise times if there are data transmission errors.

Why is the UART's maximum crystal frequency only 24MHz?

They crystal oscillator circuitry is recommended for fundamental frequency crystals only. The maximum frequency for crystals with fundamental frequencies is typically 24MHz. Above that frequency, crystals operate at higher harmonics, which will not work with the recommended crystal oscillator circuitry.

Is a clock on XTAL1 required to access the internal UART registers?

No. It is only required for transmitting and receiving data.

What is the difference between LSR bit-6 and LSR bit-5?

LSR bit-6 is a superset of LSR bit-5. The transmitter consists of a TX FIFO (or THR only when FIFOs are not enabled) and a Transmit Shift Register (TSR). When LSR bit-5 is set, it indicates that the TX FIFO (or THR) is empty, however there may be data in the TSR. When LSR bit-6 is set, it indicates that the transmitter (TX FIFO + TSR) is completely empty.

Can I use a non-standard clock frequency with the UART and still transmit/receive at standard baud rates?

Yes, if you are using a UART with a fractional baud rate generator. This provides a divisor feature with a granularity of 1/16, allowing for any baud rate to be generated by any clock frequency, standard or non-standard. Click on the parametric search button of the product family page and find the Fractional Baud Rate Generator column which tells which products have this feature.

How can the UART wake-up from sleep mode?

The UART will wake-up from sleep mode by any of the following conditions on any channel:

 

-Sleep mode is disabled

-Interrupt is generated

-Data is written into THR

-There is activity on the RX input pin

-There is activity on the modem input pins

 

If the sleep mode is still enabled and all wake-up conditions have been cleared, it will return to the sleep mode.

 

See AN204, UART Sleep Mode for more information on UART Sleep Mode 

Will I receive an interrupt when the UART wakes up from sleep mode if all interrupts are disabled?

For any UART that has the wake-up indicator interrupt, an interrupt will be generated when the UART wakes up even if no other interrupts are enabled.

 

See AN204, UART Sleep Mode for more information on UART Sleep Mode 

When a Transmit interrupt is generated (ISR = 0xC2), how do I know if it was generated because the TX FIFO is below the trigger level or if the TX FIFO is empty? (This applies only to UARTs with TX FIFO Trigger Levels.)

You can tell by reading LSR bit-5 or bit-6. If they are '0', then the transmit interrupt was generated by the trigger level. If they are '1', then the transmit interrupt was generated by the TX FIFO becoming empty. For enhanced UARTs, you can just read the FIFO level counters.

What is the difference between a RX Data Ready interrupt and a RX Data Timeout interrupt?

An RX Data Ready interrupt is generated when the number of bytes in the RX FIFO has reached the RX trigger level. An RX Data Timeout interrupt is generated when the RX input has been idle for 4 character + 12 bits time.

Which interrupt has a higher priority? The RX Data Ready interrupt or RX Data Timeout interrupt?

For some UARTs, the RX Data Timeout interrupt has a higher priority and in others, the RX Data Ready interrupt has a higher priority. See the interrupt priority section of the datasheet.

I am not able to transmit or receive data, what could be wrong?

The UART requires a clock and a valid baud rate in order to transmit and receive data. Check that there is a clock signal on the XTAL1 input pin. Also, valid divisors need to be written into the DLL and DLM registers. Most UARTs have random (invalid) values upon power-up.

If a character with an error is received, is an LSR interrupt generated immediately or when the character is ready to be read from the RX FIFO?

For most UARTs, the interrupt is generated when the data is ready to be read from the RX FIFO. The are some UARTs that generate the interrupt when the character with the error is received. There are some UARTs that have a register bit to select whether the LSR interrupt is generated immediately or delayed until it is ready to be read.

Do I need to enable both the UART's Auto RTS and Auto CTS?

No, Auto RTS and Auto CTS are independent. Auto RTS is toggled by the UART receiver. Auto CTS is monitored by the UART Transmitter.

Do I need to enable the UART's Auto RTS and Auto CTS interrupts for Auto RTS and Auto CTS to function properly?

No, Auto RTS and Auto CTS will work normally without the interrupts enabled.

What conditions are required for enabling the sleep mode in UARTs?

The UART will enter the sleep mode if the following conditions have been satisfied for all channels:

 

-Sleep Mode is enabled

-No interrupts are pending

-TX and RX FIFOs are empty

-RX input pin is idling HIGH (LOW in IR mode)

-Valid values in DLL and DLM registers

-Modem input pins are idle (MSR bits 3-0=0x0)

 

See AN204, UART Sleep Mode for more information on UART Sleep Mode

How can I tell if the UART is in the sleep mode?

There will be no activity on the XTAL2 output.

 

See AN204, UART Sleep Mode for more information on UART Sleep Mode 

Are software flow control characters loaded into the RX FIFO of the UART?

No, software flow control characters are not loaded into the RX FIFO.

Can I use Auto RTS flow control when Auto RS485 Half-Duplex Control is used?

Auto RS485 Half-Duplex Control feature overrides the Auto RTS flow control feature if both features use the RTS# output pin. Both features can only be used simultaneously if the Auto RS485 control output is not the RTS# output. For some UARTs, the Auto RS485 control output is not the RTS# output.

In Auto RS485 Half-Duplex control, which 8-bit / VLIO UARTs can use some other outputs besides RTS# as the RS485 control output?

Most UARTs use RTS#, however the XR16C850 and XR16C864 use the OP1# output as the Auto RS485 control output. In addition to using the RTS# output as the Auto RS485 control output, the XR16L784, XR16L788 and XR16V798 can use the DTR# output as the Auto RS485 control output.

What is the advantage of using the UART's 2-character software flow control?

Since 2-character software flow control requires that 2 consecutive flow control characters match before data transmission is stopped or resumes, there is less of a chance that data transmission is stopped because one data byte matched a control character.

In Auto RS485 Half-Duplex control, what is the polarity of the RS485 control output?

The polarity of the RS485 control output varies from one UART to another. For some UARTs, an inverter may be required. Some of the newer UARTs have register bits that can change that polarity of the RS485 control output.

In some UARTs, there are 2 sets of FIFO counters. One set is located at the Scratchpad Register location and the other is accessible when LCR = 0xBF. Which one should I use?

It is recommended that the FIFO counters at the Scratchpad Register location be used. When transmitting or receiving data, writing to the LCR register could result in transmit and/or receive data errors.

What is the recommended way for reading the FIFO Counters in the UART?

Due to the dynamic nature of the FIFO counters, it is recommended that the FIFO counter registers be read until consecutive reads return the same value.

In Auto RS485 Half-Duplex control, how does enabling the RS485 mode change the behavior of the interrupt?

In the normal mode, the TX interrupt is generated when the TX FIFO is empty, and there may still be data in the Transmit Shift Register. In the RS485 mode, the TX interrupt is generated when the TX FIFO and the TSR register are both empty.

What is the maximum data rate supported by the IR Mode in the UART?

All of the UARTs that have the IR mode supports up to 115.2Kbps as specified in IrDA 1.0. The newer I2C/SPI UARTs can support up to 1.152Mbps as specified in IrDA 1.1.

Can registers be read or written to in sleep mode?

Yes. Note: some devices do have powersave mode. If UART goes into powersave mode, then the registers are not accessible.

 

See more on Sleep Mode in AN204 UART Sleep Mode.

After the UART wakes up, it can't transmit and receive data. What should be checked?

 

• Check whether the register set can be accessed.
• Check whether the crystal is oscillating fully.
• Check whether the data can be transmitted in internal loopback mode.

 

 

See more on Sleep Mode in AN204 UART Sleep Mode.

What does the -F suffix on the part number mean?

The -F suffix indicates ROHS / Green compliance:
https://www.exar.com/quality-assurance-and-reliability/lead-free-program

After enabling sleep mode, the UART isn't going to sleep. Why?

Please check that all the following conditions are satisfied first.

 

• no interrupts pending (ISR bit-0 = 1)
• modem inputs are not toggling (MSR bits 0-3 = 0)
• RX input pin is idling HIGH • divisor (the value in DLL register) is non-zero
• TX and RX FIFOs are empty

 

Be sure sleep mode bit has been set to 1. If there are multiple UART channels, the sleep conditions must be true for all channels.

 

See more on Sleep Mode in AN204 UART Sleep Mode.

Writing a byte of data to the UART doesn't wake it from sleep mode. Why?

Read LSR register to check whether the UART receives the data or not.

 

• If LSR value is 0x60, it means that either UART receiver FIFO doesn’t receive the data or the data in receiver FIFO has been read out before the read of LSR.
• If LSR value is 0x00, it means data is still in the THR (clock doesn’t oscillate to transmit data).
• If LSR value is 0xFF, it means either UART is in powersave mode or UART is powered off. For those devices with powersave mode, be sure that UARTS are not in powersave mode.

 

 

See more on Sleep Mode in AN204 UART Sleep Mode.