XR16C2852
Overview
Information | Dual UART with TX and RX FIFO Counters, 128-Byte FIFO and Automatic RS-485 Half Duplex Control |
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Data Bus Interface | Intel |
# of Channels | 2 |
Max Data Rate 5V (Mbps) | 3.125 |
Max Data Rate 3.3V (Mbps) | 2 |
Max Data Rate 2.5V (Mbps) | na |
Max Data Rate 1.8V (Mbps) | na |
Tx FIFO (Bytes) | 128 |
Rx FIFO (Bytes) | 128 |
Auto Flow Control | ✔ |
Auto RS-485 Half-Duplex Control | ✔ |
Multidrop (9-bit) Mode | |
Fractional Baud Rate Generator | |
Power Down Mode | ✔ |
Supply Voltage Range VCC (V) | 2.97 to 5.5 |
Auto RTS/CTS | ✔ |
Package | PLCC-44 |
FIFO Level Counters | ✔ |
Selectable/ Programable Trigger Levels | P |
IrDA Sup | ✔ |
5V Tolerant Inputs | ✔ |
Max UART/GPIO Input Voltage (V) | 5.5 |
Max UART/GPIO Output Voltage (V) | VCC |
Temperature Range (°C) | -40 to 85 |
The XR16C2852 (2852) is a dual universal asynchronous receiver and transmitter (UART). The 2852 provides enhanced UART functions with 128 byte FIFO, automatic RS-485 half duplex control, a modem control interface, and data rates up to 1.5 Mbps. Onboard status registers provide the user with error indications and operational status. An alternate function register supports concurrent write to UART A and B. System interrupts and modem control features may be tailored by external software to meet specific user requirements.
An internal loopback capability allows onboard diagnostics. Independent programmable baud rate generators are provided to select transmit and receive clock rates up to 1.5 Mbps. The baud rate generator can be configured for either crystal or external clock input. The 2852 is available in a 44-pin PLCC package and functionally compatible with the ST16C2552. The 2852 is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements.
- Pin and functionally compatible to ST16C2552, and National PC16552/NS16C552
- Independent channel A/B control
- Up to 1.5 Mbps data rate operation
- 128 byte transmit FIFO to reduce CPU bandwidth requirement
- 128 byte receive FIFO with error flags to reduce CPU bandwdth requirement
- Programmable transmit and receive FIFO trigger level from 0 to 127
- Automatic RTS/CTS flow control with hysteresis
- Automatic software flow control
- Automatic RS485 half duplex direction control on -RTS pin
- Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD, and software controllable line break)
- Infrared (IrDA ver 1.0) transmit and receive data encoder/decoder
- Device identification and revision
- Standard 460.8 Kbps transmit/receive data rate with 7.3728 MHz crystal or external clock source
- +5V or 3.3V operation
- Industrial and commercial temperature grades
- 44-pin PLCC package
- Pb-Free, RoHS Compliant Versions Offered
- Portable Appliances
- Telecommunication Network Routers
- Ethernet Network Routers
- Cellular Data Devices
- Factory Automation and Process Controls
Documentation & Design Tools
Type | Title | Version | Date | File Size |
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Data Sheets | XR16C2852 2.97V to 5.5V Dual UART with 128-Byte FIFOS | 2.1.1 | February 2005 | 853.5 KB |
Application Notes | DAN-190, MaxLinear UARTs in RS-485 Applications | R01 | July 2023 | 2.4 MB |
Application Notes | AN-204, UART Sleep Mode | 1.0.0 | June 2010 | 515.8 KB |
Application Notes | DAN-162, Migrating from XR16C2852 to XR16L2752 | 1.0.0 | August 2002 | 17.2 KB |
Application Notes | DAN-108, UART Crystal Oscillator Design Guide | 1.0.0 | March 2000 | 218.1 KB |
Application Notes | DAN-107, Interfacing 16Cxxx UARTs to a CPU | 1.0.0 | August 1999 | 32.4 KB |
User Guides & Manuals | Evaluation Board User's Manual | 1.3.0 | August 2003 | 24.7 KB |
Product Brochures | Interface Brochure | R01 | June 2024 | 3.6 MB |
Schematics & Design Files | ISA Eval Board Schematic | 1.4.0 | August 2007 | 109 KB |
Schematics & Design Files | PCI Eval Board Schematic | 1.1.0 | July 2007 | 167.8 KB |
Software: Drivers | Linux 2.6.13 | 1.0.0 | December 2009 | 10.8 KB |
Software: Drivers | Linux 2.6.18 | 1.0.0 | December 2009 | 12.1 KB |
Software: Drivers | Windows XP & 2000 | 1.3.0.0 | December 2009 | 61 KB |
Quality & RoHS
Part Number | RoHS | Exempt | RoHS | Halogen Free | REACH | TSCA | MSL Rating / Peak Reflow | Package |
---|---|---|---|---|---|---|---|
XR16C2852CJ-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC44 |
XR16C2852IJ-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC44 |
XR16C2852IJTR-F | N | Y | Y | Y | Y | L1 / 260ᵒC | PLCC44 |
Click on the links above to download the Certificate of Non-Use of Hazardous Substances.
Parts & Purchasing
Part Number | Pkg Code | Min Temp | Max Temp | Status | Suggested Replacement | Buy Now | Order Samples | PDN |
---|---|---|---|---|---|---|---|---|
XR16C2852CJ-F | PLCC44 | 0 | 70 | Active | Order | |||
XR16C2852CJTR-F | PLCC44 | 0 | 70 | OBS | XR16C2852CJ-F | |||
XR16C2852IJ-F | PLCC44 | -40 | 85 | Active | Order | |||
XR16C2852IJTR-F | PLCC44 | -40 | 85 | Active | Order |
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.
Packaging
Pkg Code | Details | Quantities | Dimensions |
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PLCC44 |
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Notifications
FAQs & Support
Search our list of FAQs for answers to common technical questions.
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Please check that all the following conditions are satisfied first.
- no interrupts pending (ISR bit-0 = 1)
- modem inputs are not toggling (MSR bits 0-3 = 0)
- RX input pin is idling HIGH • divisor (the value in DLL register) is non-zero
- TX and RX FIFOs are empty
Be sure sleep mode bit has been set to 1. If there are multiple UART channels, the sleep conditions must be true for all channels.
See more on Sleep Mode in AN204 UART Sleep Mode.
Yes. Note: some devices do have powersave mode. If UART goes into powersave mode, then the registers are not accessible.
See more on Sleep Mode in AN204 UART Sleep Mode.
Read LSR register to check whether the UART receives the data or not.
- If LSR value is 0x60, it means that either UART receiver FIFO doesn’t receive the data or the data in receiver FIFO has been read out before the read of LSR.
- If LSR value is 0x00, it means data is still in the THR (clock doesn’t oscillate to transmit data).
- If LSR value is 0xFF, it means either UART is in powersave mode or UART is powered off. For those devices with powersave mode, be sure that UARTS are not in powersave mode.
See more on Sleep Mode in AN204 UART Sleep Mode.
- Check whether the register set can be accessed.
- Check whether the crystal is oscillating fully.
- Check whether the data can be transmitted in internal loopback mode.
See more on Sleep Mode in AN204 UART Sleep Mode.
Videos
MxL UARTs Auto RS-485 Direction Control
This video describes how the automatic RS-485 half-duplex direction control feature in MaxLinear UARTs reduces driver development and frees up CPU/MCU loading. This feature eliminates the need to monitor the status of the UART’s transmit shift register and automatically switches MaxLinear RS-485 transceivers from the transmit mode to the receive mode. This video summarizes the content in application note DAN-190.