XR16C854
Overview
Information | Quad UART with RX/TX FIFO Counters and 128-Byte FIFO |
---|---|
Data Bus Interface | Intel, Motorola |
# of Channels | 4 |
Max Data Rate 5V (Mbps) | 2 |
Max Data Rate 3.3V (Mbps) | 1.5 |
Max Data Rate 2.5V (Mbps) | na |
Max Data Rate 1.8V (Mbps) | na |
Tx FIFO (Bytes) | 128 |
Rx FIFO (Bytes) | 128 |
Auto Flow Control | ✔ |
Auto RS-485 Half-Duplex Control | ✔ |
Multidrop (9-bit) Mode | |
Fractional Baud Rate Generator | |
Power Down Mode | ✔ |
Supply Voltage Range VCC (V) | 2.97 to 5.5 |
Auto RTS/CTS | ✔ |
Package | QFP-100, LQFP-64 |
FIFO Level Counters | ✔ |
Selectable/ Programable Trigger Levels | P |
IrDA Sup | ✔ |
5V Tolerant Inputs | ✔ |
Max UART/GPIO Input Voltage (V) | 5.5 |
Max UART/GPIO Output Voltage (V) | VCC |
Temperature Range (°C) | -40 to 85 |
The XR16C8541 (854) is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface compatible with the ST16C554D/654 and ST68C554/654.
The 854 is an enhanced UART with 128 byte FIFOs, Independent Transmit and Receive FIFO counter, automatic hardware/software flow control, and data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status, modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics.
The 854 is available in 64 pin LQFP, 68 pin PLCC and 100 pin QFP packages. The 64 pin package offers the 16 interface mode which is compatible with the industry standard ST16C554. The 68 and 100 pin packages offer an additional 68 mode which allows easy integration with Motorola, and other popular microprocessors. The XR16C854CV (64 pin) offers three state interrupt control while the XR16C854DV provides constant active interrupt outputs.
The 64 pin devices do not offer TXRDY/RXRDY outputs or the default clock select option (CLKSEL). The 100 pin packages offer faster channel status access by providing separate outputs for TXRDY and RXRDY, offer separate Infrared TX outputs and a musical instrument clock input (MIDICLK). The 854 combines the package interface modes of the 16C554/654 and 68C554/654 series on a single integrated chip.
NOTE: 1Covered by U.S. Patent #5,649,122 and #5,949,787.
- 5 volt tolerant inputs
- 2.97 to 5.5 Volt Operation
- Pin-to-pin compatible with the industry standard ST16C554 and ST16C654 and TI’s TL16C554N and TL16C754BFN
- Intel or Motorola Data Bus Interface select
- Four independent UART channels
- Register Set Compatible to 16C550
- Data rates of up to 2 Mbps
- Transmit and Receive FIFOs of 128 bytes
- Programmable TX and RX FIFO Trigger Levels
- Transmit and Receive FIFO Level Counters
- Automatic Hardware (RTS/CTS) Flow Control
- Selectable Auto RTS Flow Control Hysteresis
- Automatic Software (Xon/Xoff) Flow Control
- Wireless Infrared (IrDA 1.0)Encoder/Decoder
- Sleep Mode (200 uA typical)
- Crystal oscillator or external clock input
- Pb-Free, RoHS Compliant Versions Offered
- Portable Appliances
- Telecommunication Network Routers
- Ethernet Network Routers
- Cellular Data Devices
- Factory Automation and Process Controls
Documentation & Design Tools
Type | Title | Version | Date | File Size |
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Data Sheets | XR16C854/854D 2.97V to 5.5V Quad UART with 128-Byte FIFO | 3.1.0 | April 2013 | 569.2 KB |
Application Notes | AN-204, UART Sleep Mode | 1.0.0 | June 2010 | 515.8 KB |
Application Notes | DAN-102, Infrared Application with ST16C580, ST16C650A or XR16C850 UART | 1.0.0 | October 2007 | 39.8 KB |
Application Notes | DAN-141, XR16C854 vs. OX16C954 | 1.0.0 | June 2002 | 21.7 KB |
Application Notes | DAN-133, ST16C554 vs TL16C554 | 1.0.0 | April 2002 | 94.4 KB |
Application Notes | DAN-108, UART Crystal Oscillator Design Guide | 1.0.0 | March 2000 | 218.1 KB |
User Guides & Manuals | XR16M654_ Evaluation Board User's Manual | 1 | April 2009 | 114.9 KB |
User Guides & Manuals | Evaluation Board User's Manual | 2.0.0 | August 2003 | 17.3 KB |
Product Brochures | Interface Brochure | R01 | June 2024 | 3.6 MB |
Schematics & Design Files | PCI Eval Board Schematic | 1.1.0 | April 2009 | 212.8 KB |
Schematics & Design Files | ISA Eval Board Schematic | 2.9.5 | August 2007 | 116.6 KB |
Simulation Models
Package Type | Vcc | Temp | Mode | Version | File |
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PLCC | 3.3V | Commercial | Intel | 1 | |
PLCC | 3.3V | Commercial | Motorola | 1 | |
PLCC | 5V | Commercial | Intel | 1 | |
PLCC | 5V | Commercial | Motorola | 1 | |
QFP | 3.3V | Commercial | Intel | 1 | |
QFP | 3.3V | Commercial | Motorola | 1 | |
QFP | 5V | Commercial | Intel | 1 | |
QFP | 5V | Commercial | Motorola | 1 | |
LQFP | 3.3V | Commercial | Intel | 1 | |
LQFP | 5V | Commercial | Intel | 1 | |
PLCC | 3.3V | Industrial | Intel | 1 | |
PLCC | 3.3V | Industrial | Motorola | 1 | |
PLCC | 5V | Industrial | Intel | 1 | |
PLCC | 5V | Industrial | Motorola | 1 | |
QFP | 3.3V | Industrial | Intel | 1 | |
QFP | 3.3V | Industrial | Motorola | 1 | |
QFP | 5V | Industrial | Intel | 1 | |
QFP | 5V | Industrial | Motorola | 1 | |
LQFP | 3.3V | Industrial | Intel | 1 | |
LQFP | 5V | Industrial | Intel | 1 |
Quality & RoHS
Part Number | RoHS | Exempt | RoHS | Halogen Free | REACH | TSCA | MSL Rating / Peak Reflow | Package |
---|---|---|---|---|---|---|---|
XR16C854CV-F | N | Y | Y | Y | Y | L3 / 260ᵒC | LQFP64 |
XR16C854IV-F | N | Y | Y | Y | Y | L3 / 260ᵒC | LQFP64 |
XR16C854CJ-F | N | Y | Y | Y | Y | L3 / 245ᵒC | PLCC68 |
XR16C854IJ-F | N | Y | Y | Y | Y | L3 / 245ᵒC | PLCC68 |
XR16C854IQ-F | N | Y | Y | Y | Y | L3 / 250ᵒC | MQFP100 14x20 |
XR16C854CQTR-F | N | Y | Y | Y | Y | L3 / 250ᵒC | MQFP100 14x20 |
Click on the links above to download the Certificate of Non-Use of Hazardous Substances.
Parts & Purchasing
Part Number | Pkg Code | Min Temp | Max Temp | Status | Suggested Replacement | Buy Now | Order Samples | PDN |
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XR16C854CJ-F | PLCC68 | 0 | 70 | OBS | XR16C854CV-F , XR16C854CQTR-F | |||
XR16C854CJTR-F | PLCC68 | 0 | 70 | OBS | XR16C854CJ-F | |||
XR16C854CQ-F | MQFP100 14x20 | 0 | 70 | OBS | XR16C854CQTR-F | |||
XR16C854CQTR-F | MQFP100 14x20 | 0 | 70 | OBS | XR16C854IQ-F | |||
XR16C854CV-F | LQFP64 | 0 | 70 | NRND | Order | |||
XR16C854CVTR-F | LQFP64 | 0 | 70 | OBS | XR16C854CV-F | |||
XR16C854IJ-F | PLCC68 | -40 | 85 | OBS | XR16C854IV-F , XR16C854IQ-F | |||
XR16C854IJTR-F | PLCC68 | -40 | 85 | OBS | XR16C854IJ-F | |||
XR16C854IQ-F | MQFP100 14x20 | -40 | 85 | NRND | Order | |||
XR16C854IQTR-F | MQFP100 14x20 | -40 | 85 | OBS | XR16C854IQ-F | |||
XR16C854IV-F | LQFP64 | -40 | 85 | NRND | Order | |||
XR16C854IVTR-F | LQFP64 | -40 | 85 | OBS | XR16C854IV-F |
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.
Packaging
Pkg Code | Details | Quantities | Dimensions |
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LQFP64 |
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MQFP100 14x20 |
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PLCC68 |
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Notifications
FAQs & Support
Search our list of FAQs for answers to common technical questions.
For material content, environmental, quality and reliability questions review the Quality tab or visit our Quality page.
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Please check that all the following conditions are satisfied first.
- no interrupts pending (ISR bit-0 = 1)
- modem inputs are not toggling (MSR bits 0-3 = 0)
- RX input pin is idling HIGH • divisor (the value in DLL register) is non-zero
- TX and RX FIFOs are empty
Be sure sleep mode bit has been set to 1. If there are multiple UART channels, the sleep conditions must be true for all channels.
See more on Sleep Mode in AN204 UART Sleep Mode.
Yes. Note: some devices do have powersave mode. If UART goes into powersave mode, then the registers are not accessible.
See more on Sleep Mode in AN204 UART Sleep Mode.
Read LSR register to check whether the UART receives the data or not.
- If LSR value is 0x60, it means that either UART receiver FIFO doesn’t receive the data or the data in receiver FIFO has been read out before the read of LSR.
- If LSR value is 0x00, it means data is still in the THR (clock doesn’t oscillate to transmit data).
- If LSR value is 0xFF, it means either UART is in powersave mode or UART is powered off. For those devices with powersave mode, be sure that UARTS are not in powersave mode.
See more on Sleep Mode in AN204 UART Sleep Mode.
- Check whether the register set can be accessed.
- Check whether the crystal is oscillating fully.
- Check whether the data can be transmitted in internal loopback mode.
See more on Sleep Mode in AN204 UART Sleep Mode.
Videos
MxL UARTs 自动 RS-485 方向控制
该视频介绍了 MaxLinear UART 中的自动 RS-485 半双工方向控制功能如何减少驱动程序开发并释放 CPU/MCU 负载。此功能无需监视 UART 发送移位寄存器的状态,并自动将 MaxLinear RS-485 收发器从发送模式切换到接收模式。该视频总结了应用说明文件 DAN-190 中的内容。