XR16C854

Quad UART with RX/TX FIFO Counters and 128-Byte FIFO

Overview

Information Quad UART with RX/TX FIFO Counters and 128-Byte FIFO
Data Bus Interface Intel, Motorola
Max Data Rate 5V (Mbps) 2
Max Data Rate 3.3V (Mbps) 1.5
Max Data Rate 2.5V (Mbps) na
Max Data Rate 1.8V (Mbps) na
Tx FIFO (Bytes) 128
Rx FIFO (Bytes) 128
Auto Flow Control
Auto RS-485 Half-Duplex Control
Multidrop (9-bit) Mode
Fractional Baud Rate Generator
Power Down Mode
Supply Voltage Range VCC (V) 2.97 to 5.5
Auto RTS/CTS
FIFO Level Counters
Selectable/ Programable Trigger Levels P
IrDA Sup
5V Tolerant Inputs
Max UART/GPIO Input Voltage (V) 5.5
Max UART/GPIO Output Voltage (V) VCC
Package QFP-100, LQFP-64
Temperature Range (°C) -40 to 85
# of Channels 4
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The XR16C8541 (854) is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface compatible with the ST16C554D/654 and ST68C554/654.

The 854 is an enhanced UART with 128 byte FIFOs, Independent Transmit and Receive FIFO counter, automatic hardware/software flow control, and data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status, modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics.

The 854 is available in 64 pin LQFP, 68 pin PLCC and 100 pin QFP packages. The 64 pin package offers the 16 interface mode which is compatible with the industry standard ST16C554. The 68 and 100 pin packages offer an additional 68 mode which allows easy integration with Motorola, and other popular microprocessors. The XR16C854CV (64 pin) offers three state interrupt control while the XR16C854DV provides constant active interrupt outputs.

The 64 pin devices do not offer TXRDY/RXRDY outputs or the default clock select option (CLKSEL). The 100 pin packages offer faster channel status access by providing separate outputs for TXRDY and RXRDY, offer separate Infrared TX outputs and a musical instrument clock input (MIDICLK). The 854 combines the package interface modes of the 16C554/654 and 68C554/654 series on a single integrated chip.

NOTE: 1Covered by U.S. Patent #5,649,122 and #5,949,787.


  • 5 volt tolerant inputs
  • 2.97 to 5.5 Volt Operation
  • Pin-to-pin compatible with the industry standard ST16C554 and ST16C654 and TI’s TL16C554N and TL16C754BFN
  • Intel or Motorola Data Bus Interface select
  • Four independent UART channels
  • Register Set Compatible to 16C550
  • Data rates of up to 2 Mbps
  • Transmit and Receive FIFOs of 128 bytes
  • Programmable TX and RX FIFO Trigger Levels
  • Transmit and Receive FIFO Level Counters
  • Automatic Hardware (RTS/CTS) Flow Control
  • Selectable Auto RTS Flow Control Hysteresis
  • Automatic Software (Xon/Xoff) Flow Control
  • Wireless Infrared (IrDA 1.0)Encoder/Decoder
  • Sleep Mode (200 uA typical)
  • Crystal oscillator or external clock input
  • Pb-Free, RoHS Compliant Versions Offered

  • Portable Appliances
  • Telecommunication Network Routers
  • Ethernet Network Routers
  • Cellular Data Devices
  • Factory Automation and Process Controls

Documentation & Design Tools

Type Title Version Date File Size
Data Sheets XR16C854/854D 2.97V to 5.5V Quad UART with 128-Byte FIFO 3.1.0 April 2013 569.2 KB
Application Notes AN-204, UART Sleep Mode 1.0.0 June 2010 515.8 KB
Application Notes DAN-102, Infrared Application with ST16C580, ST16C650A or XR16C850 UART 1.0.0 October 2007 39.8 KB
Application Notes DAN-141, XR16C854 vs. OX16C954 1.0.0 June 2002 21.7 KB
Application Notes DAN-133, ST16C554 vs TL16C554 1.0.0 April 2002 94.4 KB
Application Notes DAN-108, UART Crystal Oscillator Design Guide 1.0.0 March 2000 218.1 KB
User Guides & Manuals XR16M654_ Evaluation Board User's Manual 1 April 2009 114.9 KB
User Guides & Manuals Evaluation Board User's Manual 2.0.0 August 2003 17.3 KB
Schematics & Design Files PCI Eval Board Schematic 1.1.0 April 2009 212.8 KB
Schematics & Design Files ISA Eval Board Schematic 2.9.5 August 2007 116.6 KB
Product Brochures Interface Brochure October 2019 1.3 MB
Simulation Models
Package Type Vcc Temp Mode Version File
PLCC 3.3V Commercial Intel 1
PLCC 3.3V Commercial Motorola 1
PLCC 5V Commercial Intel 1
PLCC 5V Commercial Motorola 1
QFP 3.3V Commercial Intel 1
QFP 3.3V Commercial Motorola 1
QFP 5V Commercial Intel 1
QFP 5V Commercial Motorola 1
LQFP 3.3V Commercial Intel 1
LQFP 5V Commercial Intel 1
PLCC 3.3V Industrial Intel 1
PLCC 3.3V Industrial Motorola 1
PLCC 5V Industrial Intel 1
PLCC 5V Industrial Motorola 1
QFP 3.3V Industrial Intel 1
QFP 3.3V Industrial Motorola 1
QFP 5V Industrial Intel 1
QFP 5V Industrial Motorola 1
LQFP 3.3V Industrial Intel 1
LQFP 5V Industrial Intel 1
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Quality & RoHS

Part Number RoHS | Exempt RoHS Halogen Free REACH TSCA MSL Rating / Peak Reflow Package
XR16C854CV-F N Y Y Y Y LQFP64 Y
XR16C854IV-F N Y Y Y Y LQFP64 Y
XR16C854CJ-F N Y Y Y Y PLCC68 Y
XR16C854IJ-F N Y Y Y Y PLCC68 Y
XR16C854IQ-F N Y Y Y Y MQFP100 14x20 Y
XR16C854CQTR-F N Y Y Y Y MQFP100 14x20 Y

Click on the links above to download the Certificate of Non-Use of Hazardous Substances.

Additional Quality Documentation may be available, please Contact Support.

Parts & Purchasing

Part Number Pkg Code Min Temp Max Temp Status Suggested Replacement Buy Now Order Samples PDN
XR16C854CJ-F PLCC68 0 70 OBS XR16C854CV-F , XR16C854CQTR-F
XR16C854CJTR-F PLCC68 0 70 OBS XR16C854CJ-F
XR16C854CQ-F MQFP100 14x20 0 70 OBS XR16C854CQTR-F
XR16C854CQTR-F MQFP100 14x20 0 70 OBS XR16C854IQ-F
XR16C854CV-F LQFP64 0 70 Active Order
XR16C854CVTR-F LQFP64 0 70 OBS XR16C854CV-F
XR16C854IJ-F PLCC68 -40 85 OBS XR16C854IV-F , XR16C854IQ-F
XR16C854IJTR-F PLCC68 -40 85 OBS XR16C854IJ-F
XR16C854IQ-F MQFP100 14x20 -40 85 Active Order
XR16C854IQTR-F MQFP100 14x20 -40 85 OBS XR16C854IQ-F
XR16C854IV-F LQFP64 -40 85 Active Order
XR16C854IVTR-F LQFP64 -40 85 OBS XR16C854IV-F
Show obsolete parts
Part Status Legend
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.

Packaging

Pkg Code Details Quantities Dimensions PDF
LQFP64
  • JEDEC Reference: MO-026
  • MSL Pb-Free: L3 @ 260ºC
  • MSL SnPb Eutectic: n/a
  • ThetaJA: 50.0ºC/W
  • Bulk Pack Style: Tray
  • Quantity per Bulk Pack: 160
  • Quantity per Reel: 1000
  • Quantity per Tube: n/a
  • Quantity per Tray: 160
  • Reel Size (Dia. x Width x Pitch): 330 x 24 x 16
  • Tape & Reel Unit Orientation: Quadrant 2
  • Dimensions: mm
  • Length: 10.00
  • Width: 10.00
  • Thickness: 1.60
  • Lead Pitch: 0.50
MQFP100 14x20
  • JEDEC Reference: MS-022
  • MSL Pb-Free: L3 @ 250°C
  • MSL SnPb Eutectic: n/a
  • ThetaJA: 45ºC/W
  • Bulk Pack Style: Tray
  • Quantity per Bulk Pack: n/a
  • Quantity per Reel: 500
  • Quantity per Tube: n/a
  • Quantity per Tray: 66
  • Reel Size (Dia. x Width x Pitch): 330 x 44 x 24
  • Tape & Reel Unit Orientation: Quadrant 1
  • Dimensions: mm
  • Length: 14.00
  • Width: 20.00
  • Thickness: 3.40
  • Lead Pitch: 0.65
PLCC68
  • JEDEC Reference: MS-018
  • MSL Pb-Free: L3 @ 245ºC
  • MSL SnPb Eutectic: n/a
  • ThetaJA: 29.0ºC/W
  • Bulk Pack Style: Tube
  • Quantity per Bulk Pack: 19
  • Quantity per Reel: 250
  • Quantity per Tube: 19
  • Quantity per Tray: n/a
  • Reel Size (Dia. x Width x Pitch): 330 x 44 x 32
  • Tape & Reel Unit Orientation: Pin 1 at sprocket hole.
  • Dimensions: mm
  • Length: 24.23
  • Width: 24.23
  • Thickness: 4.57
  • Lead Pitch: 1.27

Notifications

Distribution Date Description File
01/12/2021 Product Discontinuation Notice
04/06/2020 Product Discontinuation Notice
12/12/2018 Product Discontinuation Notice
07/12/2017 Product Discontinuation Notice
01/04/2017 Qualification of alternate assembly subcon, ANST.
07/29/2016 Qualification of alternate assembly subcon, Greatek, Taiwan.
07/26/2016 Product discontinuation notification. Discontinued.
11/05/2015 Updated information subsequent to original published PCN 13-0834-03 on 04/02/2014. ASE Malaysia as alternate assembly site Addition of qualified alternate assembly site of 28, 44, 68L PLCC packaged products.
07/18/2014 Elimination of back mark. Eliminate back mark; consolidate information in top mark.
04/02/2014 Qualification of ASE Malaysia for assembly of 28, 44, 68L PLCC packaged products. Alternate assembly site.
10/03/2013 Addition of an alternate qualified assembly site, ASE Chung-Li (Taiwan). Material change and alternate assembly site.
07/02/2013 AC Electrical Characteristics updated in datasheet. Datasheet change.
10/17/2012 Exar has qualified Millennium Microtech/Thailand as an alternate assembly supplier for 28, 44 and 68 lead PLCC packages in addition to the existing supplier, Unisem/Indonesia. Capacity enhancement

FAQs & Support

Search our list of FAQs for answers to common technical questions.
For material content, environmental, quality and reliability questions review the Quality tab or visit our Quality page.
For ordering information and general customer service visit our Contact Us page.

Submit a Technical Support Question As a New Question

LSR bit-6 is a superset of LSR bit-5. The transmitter consists of a TX FIFO (or THR only when FIFOs are not enabled) and a Transmit Shift Register (TSR). When LSR bit-5 is set, it indicates that the TX FIFO (or THR) is empty, however there may be data in the TSR. When LSR bit-6 is set, it indicates that the transmitter (TX FIFO + TSR) is completely empty.

You can tell by reading LSR bit-5 or bit-6. If they are '0', then the transmit interrupt was generated by the trigger level. If they are '1', then the transmit interrupt was generated by the TX FIFO becoming empty. For enhanced UARTs, you can just read the FIFO level counters.

An RX Data Ready interrupt is generated when the number of bytes in the RX FIFO has reached the RX trigger level. An RX Data Timeout interrupt is generated when the RX input has been idle for 4 character + 12 bits time.

For some UARTs, the RX Data Timeout interrupt has a higher priority and in others, the RX Data Ready interrupt has a higher priority. See the interrupt priority section of the datasheet.

The UART requires a clock and a valid baud rate in order to transmit and receive data. Check that there is a clock signal on the XTAL1 input pin. Also, valid divisors need to be written into the DLL and DLM registers. Most UARTs have random (invalid) values upon power-up.

For most UARTs, the interrupt is generated when the data is ready to be read from the RX FIFO. The are some UARTs that generate the interrupt when the character with the error is received. There are some UARTs that have a register bit to select whether the LSR interrupt is generated immediately or delayed until it is ready to be read.

The UART will enter the sleep mode if the following conditions have been satisfied for all channels:
 
-Sleep Mode is enabled
-No interrupts are pending
-TX and RX FIFOs are empty
-RX input pin is idling HIGH (LOW in IR mode)
-Valid values in DLL and DLM registers
-Modem input pins are idle (MSR bits 3-0=0x0)
 
See AN204, UART Sleep Mode for more information on UART Sleep Mode

The UART will wake-up from sleep mode by any of the following conditions on any channel:
 
-Sleep mode is disabled
-Interrupt is generated
-Data is written into THR
-There is activity on the RX input pin
-There is activity on the modem input pins
 
If the sleep mode is still enabled and all wake-up conditions have been cleared, it will return to the sleep mode.
 
See AN204, UART Sleep Mode for more information on UART Sleep Mode 

There will be no activity on the XTAL2 output.
 
See AN204, UART Sleep Mode for more information on UART Sleep Mode 

For any UART that has the wake-up indicator interrupt, an interrupt will be generated when the UART wakes up even if no other interrupts are enabled.
 
See AN204, UART Sleep Mode for more information on UART Sleep Mode 

No, Auto RTS and Auto CTS are independent. Auto RTS is toggled by the UART receiver. Auto CTS is monitored by the UART Transmitter.

No, Auto RTS and Auto CTS will work normally without the interrupts enabled.

No, software flow control characters are not loaded into the RX FIFO.

Since 2-character software flow control requires that 2 consecutive flow control characters match before data transmission is stopped or resumes, there is less of a chance that data transmission is stopped because one data byte matched a control character.

Auto RS485 Half-Duplex Control feature overrides the Auto RTS flow control feature if both features use the RTS# output pin. Both features can only be used simultaneously if the Auto RS485 control output is not the RTS# output. For some UARTs, the Auto RS485 control output is not the RTS# output.

Most UARTs use RTS#, however the XR16C850 and XR16C864 use the OP1# output as the Auto RS485 control output. In addition to using the RTS# output as the Auto RS485 control output, the XR16L784, XR16L788 and XR16V798 can use the DTR# output as the Auto RS485 control output.

The polarity of the RS485 control output varies from one UART to another. For some UARTs, an inverter may be required. Some of the newer UARTs have register bits that can change that polarity of the RS485 control output.

In the normal mode, the TX interrupt is generated when the TX FIFO is empty, and there may still be data in the Transmit Shift Register. In the RS485 mode, the TX interrupt is generated when the TX FIFO and the TSR register are both empty.

It is recommended that the FIFO counters at the Scratchpad Register location be used. When transmitting or receiving data, writing to the LCR register could result in transmit and/or receive data errors.

Due to the dynamic nature of the FIFO counters, it is recommended that the FIFO counter registers be read until consecutive reads return the same value.

All of the UARTs that have the IR mode supports up to 115.2Kbps as specified in IrDA 1.0. The newer I2C/SPI UARTs can support up to 1.152Mbps as specified in IrDA 1.1.

For external clock frequencies above 24MHz at the XTAL1 input, a 2K pull-up may be necessary to improve the rise times if there are data transmission errors.

Yes, you can daisy-chain it like that, but only up to 2 times (3 UARTs total in the daisy-chain). The UARTs should be as close as possible.

No, it just has to meet the minimum high and low pulse widths.

Yes, if you are using a UART with a fractional baud rate generator. This provides a divisor feature with a granularity of 1/16, allowing for any baud rate to be generated by any clock frequency, standard or non-standard. Click on the parametric search button of the product family page and find the Fractional Baud Rate Generator column which tells which products have this feature.

They crystal oscillator circuitry is recommended for fundamental frequency crystals only. The maximum frequency for crystals with fundamental frequencies is typically 24MHz. Above that frequency, crystals operate at higher harmonics, which will not work with the recommended crystal oscillator circuitry.

No. It is only required for transmitting and receiving data.

The -F suffix indicates ROHS / Green compliance:
https://www.exar.com/quality-assurance-and-reliability/lead-free-program

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It depends on the baud rate. For example, for a start bit, 8 data bits, no stop bit and 1 stop bit, the maximum baud rate deviation is 4.76%. For more information, see https://www.exar.com/appnote/dan108.pdf

Please check that all the following conditions are satisfied first.

 

  • no interrupts pending (ISR bit-0 = 1)
  • modem inputs are not toggling (MSR bits 0-3 = 0)
  • RX input pin is idling HIGH • divisor (the value in DLL register) is non-zero
  • TX and RX FIFOs are empty

 

Be sure sleep mode bit has been set to 1. If there are multiple UART channels, the sleep conditions must be true for all channels.

 

See more on Sleep Mode in AN204 UART Sleep Mode.

Yes. Note: some devices do have powersave mode. If UART goes into powersave mode, then the registers are not accessible.

 

See more on Sleep Mode in AN204 UART Sleep Mode.

Read LSR register to check whether the UART receives the data or not.

 

  • If LSR value is 0x60, it means that either UART receiver FIFO doesn’t receive the data or the data in receiver FIFO has been read out before the read of LSR.
  • If LSR value is 0x00, it means data is still in the THR (clock doesn’t oscillate to transmit data).
  • If LSR value is 0xFF, it means either UART is in powersave mode or UART is powered off. For those devices with powersave mode, be sure that UARTS are not in powersave mode.

 

 

See more on Sleep Mode in AN204 UART Sleep Mode.

 

  • Check whether the register set can be accessed.
  • Check whether the crystal is oscillating fully.
  • Check whether the data can be transmitted in internal loopback mode.

 

 

See more on Sleep Mode in AN204 UART Sleep Mode.