Overview
Information | 1.62V TO 3.63V Quad UART WITH 32-Byte FIFO |
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Data Bus Interface | Intel, Motorola |
# of Channels | 4 |
Max Data Rate 5V (Mbps) | na |
Max Data Rate 3.3V (Mbps) | 16 |
Max Data Rate 2.5V (Mbps) | 12.5 |
Max Data Rate 1.8V (Mbps) | 8 |
Tx FIFO (Bytes) | 32 |
Rx FIFO (Bytes) | 32 |
Auto Flow Control | ✔ |
Auto RS-485 Half-Duplex Control | |
Multidrop (9-bit) Mode | |
Fractional Baud Rate Generator | ✔ |
Power Down Mode | ✔ |
Supply Voltage Range VCC (V) | 1.62 to 3.63 |
Auto RTS/CTS | ✔ |
Package | LQFP-64 |
FIFO Level Counters | |
Selectable/ Programable Trigger Levels | S |
IrDA Sup | ✔ |
5V Tolerant Inputs | |
Max UART/GPIO Input Voltage (V) | VCC |
Max UART/GPIO Output Voltage (V) | VCC |
Temperature Range (°C) | -40 to 85 |
The XR16M564¹ (M564) is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) with 32 bytes of transmit and receive FIFOs, programmable transmit and receive FIFO trigger levels, automatic hardware and software flow control, and data rates of up to 16 Mbps at 4X sampling rate. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The M564 is available in a 48-pin QFN, 64-pin LQFP, 68-pin PLCC and 80-pin LQFP packages. The 64-pin and 80-pin packages only offer the 16 mode interface, but the 48 and 68 pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors. The XR16M564IV (64-pin) offers three state interrupt output while the XR16M564DIV provides continuous interrupt output. The XR16M564 is compatible with the industry standard ST16C554 and ST16C654/654D.
NOTE: ¹Covered by U.S. Patent #5,649,122.
- Pin-to-pin compatible with ST16C454, ST16C554, TI's TL16C754B and NXP's SC16C754B
- Intel or Motorola Data Bus Interface select
- Four independent UART channels
- Register Set Compatible to 16C550
- Data rates of up to 16 Mbps
- 32 byte Transmit FIFO
- 32 byte Receive FIFO with error tags
- 4 Selectable TX and RX FIFO Trigger Levels
- Automatic Hardware (RTS/CTS) Flow Control
- Automatic Software (Xon/Xoff) Flow Control
- Programmable Xon/Xoff characters
- Wireless Infrared (IrDA 1.0) Encoder/Decoder
- Full modem interface
- 1.62V to 3.63V supply operation
- Sleep Mode with automatic wake-up
- Crystal oscillator or external clock input
- Pb-Free, RoHS Compliant Versions Offered
- Portable Appliances
- Telecommunication Network Routers
- Ethernet Network Routers
- Cellular Data Devices
- Factory Automation and Process Controls
Documentation & Design Tools
Type | Title | Version | Date | File Size |
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Data Sheets | XR16M564/564D 1.62V to 3.63V Quad UART with 32-Byte FIFO | 1.0.0 | May 2008 | 1.1 MB |
Application Notes | AN-204, UART Sleep Mode | 1.0.0 | June 2010 | 515.8 KB |
Application Notes | DAN-189, MaxLinear UARTs in GPS Applications | 1.0.0 | April 2008 | 139 KB |
User Guides & Manuals | XR16M654_ Evaluation Board User's Manual | 1 | April 2009 | 114.9 KB |
Product Brochures | Interface Brochure | R01 | June 2024 | 3.6 MB |
Schematics & Design Files | PCI Eval Board Schematic | 1.1.0 | April 2009 | 212.8 KB |
Schematics & Design Files | ISA Eval Board Schematic | 1.1.0 | September 2007 | 187.4 KB |
Quality & RoHS
Parts & Purchasing
Part Number | Pkg Code | Min Temp | Max Temp | Status | Suggested Replacement | PDN |
---|---|---|---|---|---|---|
XR16M564IJ68-F | PLCC68 | -40 | 85 | OBS | XR16M564IV64-F | |
XR16M564IJ68TR-F | PLCC68 | -40 | 85 | OBS | XR16M564IV64-F | |
XR16M564IL48-F | QFN48 7x7 | -40 | 85 | OBS | XR16M654IL48-F | |
XR16M564IL48TR-F | QFN48 7x7 | -40 | 85 | OBS | XR16M564IL48-F | |
XR16M564IV64-F | LQFP64 | -40 | 85 | OBS | ||
XR16M564IV64TR-F | LQFP64 | -40 | 85 | OBS | XR16M564IV64-F | |
XR16M564IV80-F | LQFP80 12x12 | -40 | 85 | OBS | XR16M554IV80-F | |
XR16M564IV80TR-F | LQFP80 12x12 | -40 | 85 | OBS | XR16M554IV80-F |
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.
Packaging
Pkg Code | Details | Quantities | Dimensions |
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LQFP64 |
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LQFP80 12x12 |
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PLCC68 |
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QFN48 7x7 |
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Notifications
FAQs & Support
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Please check that all the following conditions are satisfied first.
- no interrupts pending (ISR bit-0 = 1)
- modem inputs are not toggling (MSR bits 0-3 = 0)
- RX input pin is idling HIGH • divisor (the value in DLL register) is non-zero
- TX and RX FIFOs are empty
Be sure sleep mode bit has been set to 1. If there are multiple UART channels, the sleep conditions must be true for all channels.
See more on Sleep Mode in AN204 UART Sleep Mode.
Yes. Note: some devices do have powersave mode. If UART goes into powersave mode, then the registers are not accessible.
See more on Sleep Mode in AN204 UART Sleep Mode.
Read LSR register to check whether the UART receives the data or not.
- If LSR value is 0x60, it means that either UART receiver FIFO doesn’t receive the data or the data in receiver FIFO has been read out before the read of LSR.
- If LSR value is 0x00, it means data is still in the THR (clock doesn’t oscillate to transmit data).
- If LSR value is 0xFF, it means either UART is in powersave mode or UART is powered off. For those devices with powersave mode, be sure that UARTS are not in powersave mode.
See more on Sleep Mode in AN204 UART Sleep Mode.
- Check whether the register set can be accessed.
- Check whether the crystal is oscillating fully.
- Check whether the data can be transmitted in internal loopback mode.
See more on Sleep Mode in AN204 UART Sleep Mode.