The XR16M654¹ (M654) is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) each with 64 bytes of transmit and receive FIFOs, programmable transmit and receive FIFO trigger levels, automatic hardware and software flow control, and data rates of up to 16 Mbps at 4X sampling rate. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The M654 is available in a 48-pin QFN, 64-pin LQFP, 68-pin PLCC, 80-pin LQFP and 100-pin QFP packages. The 64-pin and 80-pin packages only offer the 16 mode interface, but the 48, 68 and 100 pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors. The XR16M654IV (64-pin) offers three state interrupt output while the XR16M654DIV provides continuous interrupt output. The 100 pin package provides additional FIFO status outputs (TXRDY# and RXRDY# A-D), separate infrared transmit data outputs (IRTX A-D) and channel C external clock input (CHCCLK). The XR16M654 is compatible with the industry standard ST16C554 and ST16C654/654D. NOTE: ¹Covered by U.S. Patent #5,649,122.
Pin-to-pin compatible with ST16C454, ST16C554, TI's TL16C754B and NXP's SC16C654B
Part Status Legend Active - the part is released for sale, standard product. EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock. CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply. PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only. OBS (Obsolete) - the part is no longer being manufactured and may not be ordered. NRND (Not Recommended for New Designs) - the part is not recommended for new designs.
Packaging
Pkg Code
Details
Quantities
Dimensions
PDF
LQFP64
JEDEC Reference: MO-026
MSL Pb-Free: L3 @ 260ºC
MSL SnPb Eutectic: n/a
ThetaJA: 50.0ºC/W
Bulk Pack Style: Tray
Quantity per Bulk Pack: 160
Quantity per Reel: 1000
Quantity per Tube: n/a
Quantity per Tray: 160
Reel Size (Dia. x Width x Pitch): 330 x 24 x 16
Tape & Reel Unit Orientation: Quadrant 2
Dimensions: mm
Length: 10.00
Width: 10.00
Thickness: 1.60
Lead Pitch: 0.50
LQFP80 12x12
JEDEC Reference: MS-026
MSL Pb-Free: L3 @ 260°C
MSL SnPb Eutectic: n/a
ThetaJA: 41ºC/W
Bulk Pack Style: Tray
Quantity per Bulk Pack: n/a
Quantity per Reel: 1000
Quantity per Tube: n/a
Quantity per Tray: 119
Reel Size (Dia. x Width x Pitch): 330 x 24 x 20
Tape & Reel Unit Orientation: Pin 1 at sprocket hole.
Dimensions: mm
Length: 12.00
Width: 12.00
Thickness: 1.60
Lead Pitch: 0.50
MQFP100 14x20
JEDEC Reference: MS-022
MSL Pb-Free: L3 @ 250°C
MSL SnPb Eutectic: n/a
ThetaJA: 45ºC/W
Bulk Pack Style: Tray
Quantity per Bulk Pack: n/a
Quantity per Reel: 500
Quantity per Tube: n/a
Quantity per Tray: 66
Reel Size (Dia. x Width x Pitch): 330 x 44 x 24
Tape & Reel Unit Orientation: Quadrant 1
Dimensions: mm
Length: 14.00
Width: 20.00
Thickness: 3.40
Lead Pitch: 0.65
PLCC68
JEDEC Reference: MS-018
MSL Pb-Free: L3 @ 245ºC
MSL SnPb Eutectic: n/a
ThetaJA: 29.0ºC/W
Bulk Pack Style: Tube
Quantity per Bulk Pack: 19
Quantity per Reel: 250
Quantity per Tube: 19
Quantity per Tray: n/a
Reel Size (Dia. x Width x Pitch): 330 x 44 x 32
Tape & Reel Unit Orientation: Pin 1 at sprocket hole.
Dimensions: mm
Length: 24.23
Width: 24.23
Thickness: 4.57
Lead Pitch: 1.27
QFN48 7x7
JEDEC Reference: MO-220
MSL Pb-Free: L3 @ 260ºC
MSL SnPb Eutectic: n/a
ThetaJA: 30.2ºC/W
Bulk Pack Style: Tray
Quantity per Bulk Pack: n/a
Quantity per Reel: 2500
Quantity per Tube: n/a
Quantity per Tray: 260
Reel Size (Dia. x Width x Pitch): 330 x 16 x 12
Tape & Reel Unit Orientation: Pin 1 at sprocket hole.
Dimensions: mm
Length: 7.00
Width: 7.00
Thickness: 1.00
Lead Pitch: 0.50
Notifications
Distribution Date
Description
File
01/23/2024
Product Discontinuation Notice
04/12/2017
Qualification of alternate assembly subcon, ANST, China.
07/29/2016
Qualification of alternate assembly subcon, Greatek, Taiwan.
Updated information subsequent to original published PCN 13-0834-03 on 04/02/2014. ASE Malaysia as alternate assembly site Addition of qualified alternate assembly site of 28, 44, 68L PLCC packaged products.
04/02/2014
Qualified UTAC Thailand for assembly using copper wire or gold wire bonding assembly, in addition to the current qualified gold wire bonding assembly sites, Unisem Batam and UTAC China. Material change and alternate assembly site.
04/02/2014
Qualification of ASE Malaysia for assembly of 28, 44, 68L PLCC packaged products. Alternate assembly site.
12/05/2013
Addition of an alternate qualified assembly site, ASE Chung-Li (Taiwan) for assembly using copper or gold wire bonding. Material change and alternate assembly site.
10/03/2013
Addition of an alternate qualified assembly site, ASE Chung-Li (Taiwan). Material change and alternate assembly site.
10/17/2012
Exar has qualified Millennium Microtech/Thailand as an alternate assembly supplier for 28, 44 and 68 lead PLCC packages in addition to the existing supplier, Unisem/Indonesia. Capacity enhancement
FAQs & Support
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LSR bit-6 is a superset of LSR bit-5. The transmitter consists of a TX FIFO (or THR only when FIFOs are not enabled) and a Transmit Shift Register (TSR). When LSR bit-5 is set, it indicates that the TX FIFO (or THR) is empty, however there may be data in the TSR. When LSR bit-6 is set, it indicates that the transmitter (TX FIFO + TSR) is completely empty.
You can tell by reading LSR bit-5 or bit-6. If they are '0', then the transmit interrupt was generated by the trigger level. If they are '1', then the transmit interrupt was generated by the TX FIFO becoming empty. For enhanced UARTs, you can just read the FIFO level counters.
An RX Data Ready interrupt is generated when the number of bytes in the RX FIFO has reached the RX trigger level. An RX Data Timeout interrupt is generated when the RX input has been idle for 4 character + 12 bits time.
For some UARTs, the RX Data Timeout interrupt has a higher priority and in others, the RX Data Ready interrupt has a higher priority. See the interrupt priority section of the datasheet.
The UART requires a clock and a valid baud rate in order to transmit and receive data. Check that there is a clock signal on the XTAL1 input pin. Also, valid divisors need to be written into the DLL and DLM registers. Most UARTs have random (invalid) values upon power-up.
For most UARTs, the interrupt is generated when the data is ready to be read from the RX FIFO. The are some UARTs that generate the interrupt when the character with the error is received. There are some UARTs that have a register bit to select whether the LSR interrupt is generated immediately or delayed until it is ready to be read.
The UART will enter the sleep mode if the following conditions have been satisfied for all channels:
No, Auto RTS and Auto CTS are independent. Auto RTS is toggled by the UART receiver. Auto CTS is monitored by the UART Transmitter.
No, Auto RTS and Auto CTS will work normally without the interrupts enabled.
No, software flow control characters are not loaded into the RX FIFO.
Since 2-character software flow control requires that 2 consecutive flow control characters match before data transmission is stopped or resumes, there is less of a chance that data transmission is stopped because one data byte matched a control character.
Auto RS485 Half-Duplex Control feature overrides the Auto RTS flow control feature if both features use the RTS# output pin. Both features can only be used simultaneously if the Auto RS485 control output is not the RTS# output. For some UARTs, the Auto RS485 control output is not the RTS# output.
Most UARTs use RTS#, however the XR16C850 and XR16C864 use the OP1# output as the Auto RS485 control output. In addition to using the RTS# output as the Auto RS485 control output, the XR16L784, XR16L788 and XR16V798 can use the DTR# output as the Auto RS485 control output.
The polarity of the RS485 control output varies from one UART to another. For some UARTs, an inverter may be required. Some of the newer UARTs have register bits that can change that polarity of the RS485 control output.
In the normal mode, the TX interrupt is generated when the TX FIFO is empty, and there may still be data in the Transmit Shift Register. In the RS485 mode, the TX interrupt is generated when the TX FIFO and the TSR register are both empty.
It is recommended that the FIFO counters at the Scratchpad Register location be used. When transmitting or receiving data, writing to the LCR register could result in transmit and/or receive data errors.
Due to the dynamic nature of the FIFO counters, it is recommended that the FIFO counter registers be read until consecutive reads return the same value.
All of the UARTs that have the IR mode supports up to 115.2Kbps as specified in IrDA 1.0. The newer I2C/SPI UARTs can support up to 1.152Mbps as specified in IrDA 1.1.
For external clock frequencies above 24MHz at the XTAL1 input, a 2K pull-up may be necessary to improve the rise times if there are data transmission errors.
Yes, you can daisy-chain it like that, but only up to 2 times (3 UARTs total in the daisy-chain). The UARTs should be as close as possible.
No, it just has to meet the minimum high and low pulse widths.
Yes, if you are using a UART with a fractional baud rate generator. This provides a divisor feature with a granularity of 1/16, allowing for any baud rate to be generated by any clock frequency, standard or non-standard. Click on the parametric search button of the product family page and find the Fractional Baud Rate Generator column which tells which products have this feature.
They crystal oscillator circuitry is recommended for fundamental frequency crystals only. The maximum frequency for crystals with fundamental frequencies is typically 24MHz. Above that frequency, crystals operate at higher harmonics, which will not work with the recommended crystal oscillator circuitry.
No. It is only required for transmitting and receiving data.
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It depends on the baud rate. For example, for a start bit, 8 data bits, no stop bit and 1 stop bit, the maximum baud rate deviation is 4.76%. For more information, see https://www.exar.com/appnote/dan108.pdf
Please check that all the following conditions are satisfied first.
no interrupts pending (ISR bit-0 = 1)
modem inputs are not toggling (MSR bits 0-3 = 0)
RX input pin is idling HIGH • divisor (the value in DLL register) is non-zero
TX and RX FIFOs are empty
Be sure sleep mode bit has been set to 1. If there are multiple UART channels, the sleep conditions must be true for all channels.
Read LSR register to check whether the UART receives the data or not.
If LSR value is 0x60, it means that either UART receiver FIFO doesn’t receive the data or the data in receiver FIFO has been read out before the read of LSR.
If LSR value is 0x00, it means data is still in the THR (clock doesn’t oscillate to transmit data).
If LSR value is 0xFF, it means either UART is in powersave mode or UART is powered off. For those devices with powersave mode, be sure that UARTS are not in powersave mode.
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