XR28V382

3.3V Dual LPC UART with 128-Byte FIFO
Data Sheets OBS (Obsolete)

Overview

Information 3.3V Dual LPC UART with 128-Byte FIFO
Data Bus Interface Intel LPC
# of Channels 2
Max Data Rate (Mbps) 3
Tx/Rx FIFO (Bytes) 128/128
Auto Flow Control
Auto RS-485 Half-Duplex Control
Multidrop (9-bit) Mode
Watchdog Timer
Power Down Mode
5V Tolerant Inputs
Supply Voltage Range VCC (V) 3 to 3.6
Max UART/GPIO Input Voltage (V) 5.5
Max UART/GPIO Output Voltage (V) VCC
Temperature Range (°C) -40 to 85
Package QFN-32
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The XR28V382 (V382) is a dual Universal Asynchronous Receiver and Transmitter (UART) for the Intel Low Pin Count (LPC) bus interface. This device can replace or supplement a Super I/O device to add additional serial ports to the system.

The V382 UARTs support any 16-bit I/O address supported by the system. The register set is based on the industry standard 16550 UART, so the V382 operates with standard serial port drivers without requiring a custom driver to be installed.

The 128 byte Transmit and Receive FIFOs reduce CPU overhead and minimize the chance of buffer overflow and data loss. In addition to the 16550 UART registers, there are also Configuration register set where enhanced features such as the 9-bit (multidrop) mode, IrDA mode and the Watchdog Timer can be enabled.

The V382 is available in a 32-pin QFN package.

  • 128 Byte Transmit and Receive FIFO
  • Compliant to LPC 1.1 Specifications
  • -40°C to +85°C Industrial Temp Operation
  • Watchdog Timer with WDTOUT# signal
  • 2 independent UART channels
    • Programmable I/O mapped base addresses
    • Data rates up to 3 Mbps
    • Selectable RX FIFO interrupt trigger levels
    • Auto RS-485 Half-Duplex Control mode
    • Programmable character lengths (5, 6, 7, 8) with even, odd, or no parity
    • IrDA mode and separate IRTXA# and IRRXA# pins for the first UART channel
    • 9-bit (Multidrop) mode
  • External 24MHz/48MHz clock
  • Single 3.3V Supply Voltage ( ± 10%)
  • 5V tolerant inputs
  • 32-QFN package (5mm x 5mm)

  • Industrial and Embedded PCs
  • Factory Automation and Process Controls
  • Network Routers
  • System Board Designs

Documentation & Design Tools

Type Title Version Date File Size
Data Sheets XR28V382 3.3V Dual LPC UART with 128-Byte FIFO 1.0.2 March 2018 2.4 MB
Application Notes DAN-190, MaxLinear UARTs in RS-485 Applications R01 July 2023 2.4 MB
User Guides & Manuals XR28V384/XR28V382 Evaluation Board User's Manual R00 August 2020 2.7 MB
Errata XR28V38X Errata 1A November 2017 641 KB
Product Brochures Interface Brochure November 2023 3.7 MB
Schematics & Design Files XR28V382-0A Evaluation Board Files: BRD, DSN, BOM, Schematic, Manual March 2019 1.4 MB
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Quality & RoHS

Part Number RoHS | Exempt RoHS Halogen Free REACH TSCA MSL Rating / Peak Reflow Package
XR28V382IL32-F N Y Y Y Y L2 / 260ᵒC QFN32 5x5 OPT3
XR28V382IL32TR-F N Y Y Y Y L2 / 260ᵒC QFN32 5x5 OPT3

Click on the links above to download the Certificate of Non-Use of Hazardous Substances.

Additional Quality Documentation may be available, please Contact Support.

Parts & Purchasing

Part Number Pkg Code Min Temp Max Temp Status Suggested Replacement PDN
XR28V382IL32-F QFN32 5x5 OPT3 -40 85 OBS
XR28V382IL32TR-F QFN32 5x5 OPT3 -40 85 OBS
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Part Status Legend
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.

Packaging

Pkg Code Details Quantities Dimensions
QFN32 5x5 OPT3
  • JEDEC Reference:
  • MSL Pb-Free: L2 @ 260ºC
  • MSL SnPb Eutectic:
  • ThetaJA: 30
  • Bulk Pack Style: Tray
  • Quantity per Bulk Pack: 490
  • Quantity per Reel: 3000
  • Quantity per Tube: n/a
  • Quantity per Tray: 490
  • Reel Size (Dia. x Width x Pitch): 330 x 12 x 8
  • Tape & Reel Unit Orientation: Quadrant 1
  • Dimensions: mm
  • Length: 5
  • Width: 5
  • Thickness: 1.00
  • Lead Pitch: 0.5

Notifications

Distribution Date Description File
06/14/2023 Product Discontinuation Notice
01/31/2022 To increase manufacturing capacity, MaxLinear has qualified UTL3 extension site as an alternate assembly site together with UTL1 for QFN and DFN products.
07/21/2017 Qualification of alternate assembly subcon, ANST.
01/27/2017 Qualification of alternate assembly subcon, ANST, China.

FAQs & Support

Search our list of FAQs for answers to common technical questions.
For material content, environmental, quality and reliability questions review the Quality tab or visit our Quality page.
For ordering information and general customer service visit our Contact Us page.

Submit a Technical Support Question As a New Question

LSR bit-6 is a superset of LSR bit-5. The transmitter consists of a TX FIFO (or THR only when FIFOs are not enabled) and a Transmit Shift Register (TSR). When LSR bit-5 is set, it indicates that the TX FIFO (or THR) is empty, however there may be data in the TSR. When LSR bit-6 is set, it indicates that the transmitter (TX FIFO + TSR) is completely empty.

You can tell by reading LSR bit-5 or bit-6. If they are '0', then the transmit interrupt was generated by the trigger level. If they are '1', then the transmit interrupt was generated by the TX FIFO becoming empty. For enhanced UARTs, you can just read the FIFO level counters.

An RX Data Ready interrupt is generated when the number of bytes in the RX FIFO has reached the RX trigger level. An RX Data Timeout interrupt is generated when the RX input has been idle for 4 character + 12 bits time.

For some UARTs, the RX Data Timeout interrupt has a higher priority and in others, the RX Data Ready interrupt has a higher priority. See the interrupt priority section of the datasheet.

The UART requires a clock and a valid baud rate in order to transmit and receive data. Check that there is a clock signal on the XTAL1 input pin. Also, valid divisors need to be written into the DLL and DLM registers. Most UARTs have random (invalid) values upon power-up.

For most UARTs, the interrupt is generated when the data is ready to be read from the RX FIFO. The are some UARTs that generate the interrupt when the character with the error is received. There are some UARTs that have a register bit to select whether the LSR interrupt is generated immediately or delayed until it is ready to be read.

No, Auto RTS and Auto CTS are independent. Auto RTS is toggled by the UART receiver. Auto CTS is monitored by the UART Transmitter.

No, Auto RTS and Auto CTS will work normally without the interrupts enabled.

No, software flow control characters are not loaded into the RX FIFO.

Auto RS485 Half-Duplex Control feature overrides the Auto RTS flow control feature if both features use the RTS# output pin. Both features can only be used simultaneously if the Auto RS485 control output is not the RTS# output. For some UARTs, the Auto RS485 control output is not the RTS# output.

The polarity of the RS485 control output varies from one UART to another. For some UARTs, an inverter may be required. Some of the newer UARTs have register bits that can change that polarity of the RS485 control output.

In the normal mode, the TX interrupt is generated when the TX FIFO is empty, and there may still be data in the Transmit Shift Register. In the RS485 mode, the TX interrupt is generated when the TX FIFO and the TSR register are both empty.

All of the UARTs that have the IR mode supports up to 115.2Kbps as specified in IrDA 1.0. The newer I2C/SPI UARTs can support up to 1.152Mbps as specified in IrDA 1.1.

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The -F suffix indicates ROHS / Green compliance:
https://www.exar.com/quality-assurance-and-reliability/lead-free-program

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It depends on the baud rate. For example, for a start bit, 8 data bits, no stop bit and 1 stop bit, the maximum baud rate deviation is 4.76%. For more information, see https://www.exar.com/appnote/dan108.pdf

Videos

MxL UARTs Auto RS-485 Direction Control

This video describes how the automatic RS-485 half-duplex direction control feature in MaxLinear UARTs reduces driver development and frees up CPU/MCU loading. This feature eliminates the need to monitor the status of the UART’s transmit shift register and automatically switches MaxLinear RS-485 transceivers from the transmit mode to the receive mode. This video summarizes the content in application note DAN-190.